Compressed instruction set: Difference between revisions

Revision as of 13:06, 28 March 2022

Revision as of 13:27, 1 April 2022

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===Code density===

The downside to the RISC approach is that many instructions simply do not require four bytes. For instance, the [[Logical shift|Logical Shift Left]] instruction shifts the bits in a register to the left. In the 6502, which has only a single arithmetic register A, this instruction can be represented entirely by it'sits 8-bit opcode {{code|$06}}.{{sfn|Verts|2004}} On processors with more registers, all that is needed is the opcode and register number, another 4 or 5 bits. On MIPS, for instance, the instruction needs only a 6-bit opcode and a 5-bit register number. But as is the case for most RISC designs, the instruction still takes up a full 32-bits. As these sorts of instructions are relatively common, RISC programs generally take up more memory than the same program on a variable length processor.{{sfn|Weaver|McKee|2009}}

In the 1980s, when the RISC concept was first emerging, this was a common point of complaint. As the instructions took up more room, the system would have to spend more time reading instructions from memory. It was suggested these extra accesses might actually slow the program down. Extensive [[benchmarking]] eventually demonstrated RISC was faster in almost all cases, and this argument faded. However, there are cases where memory use remains a concern regardless of performance, and that is in small systems and embedded applications. Even in the early 2000s, the price of [[DRAM]] was enough that cost-sensitive devices had limited memory. It was for this market that [[Hitachi]] developed the [[SuperH]] design.<ref>{{cite web |url=http://resource.renesas.com/lib/eng/e_learnig/sh4/02/index.html |title=Effects of 16-bit instructions |website=Renesas}}</ref>