The [[Sieve C++ Parallel Programming System|Codeplay Sieve compiler]] supports the PPU, indicating that the Ageia physX chip would be suitable for GPGPU type tasks. However Ageia seem unlikely to pursue this market.
==Intel Xeon Phi==
Like the Cell, [[Xeon Phi]] sits between the CPU and the GPU, in the spectrum between, general purpose processing versus specialized high-performance back-end processing. This uses caches rather than [[scratchpad memory|scratchpads]], but still manages to achieve high throughput.
[[Advanced Micro Devices|AMD]] have declared their long term intention to enable [[AMD Accelerated Processing Unit|AMD APUs]] to use [[Radeon]] as a vector co-processor, sharing resources such as [[cache hierarchy]]. This future configuration started materializing in the form of [[Heterogeneous System Architecture]].
