MIPS architecture processors: Difference between revisions

Revision as of 06:12, 30 March 2022

Revision as of 23:38, 23 April 2022

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[[Quantum Effect Devices]] (QED), a separate company started by former MIPS employees, designed the ''[[R4600]]'' ''Orion'', the ''[[R4700]]'' ''Orion'', the ''[[R4650]]'' and the ''[[R5000]]''. Where the R4000 had pushed clock frequency and sacrificed cache capacity, the QED designs emphasized large caches which could be accessed in just two cycles and efficient use of silicon area. The R4600 and R4700 were used in low-cost versions of the [[SGI Indy]] workstation as well as the first MIPS-based Cisco routers, such as the 36x0 and 7x00-series routers. The [[R4650]] was used in the original [[WebTV]] [[set-top box]]es (now Microsoft TV). The [[R5000]] FPU had more flexible single precision floating-point scheduling than the R4000, and as a result, R5000-based SGI Indys had much better graphics performance than similarly clocked [[R4400]] Indys with the same graphics hardware. SGI gave the old graphics board a new name when it was combined with [[R5000]], to emphasize the improvement. QED later designed the ''RM7000'' and ''[[RM9000]]'' family of devices for [[embedded system]] markets like [[computer network]]ing and laser printers. QED was acquired by the semiconductor manufacturer [[PMC-Sierra]] in August 2000, the latter company continuing to invest in the MIPS architecture. The ''[[RM7000]]'' included an integrated 256 KB L2 cache and a controller for optional L3 cache. The ''RM9xx0'' were a family of [[System-on-a-chip|SOC]] devices which included [[Northbridge (computing)|northbridge]] peripherals such as [[memory controller]], [[Peripheral Component Interconnect|PCI]] controller, [[Gigabit Ethernet]] controller and fast I/O such as a [[HyperTransport]] port.

The ''[[R8000]]'' (1994) was the first [[superscalar]] MIPS design, able to execute two integer or floating point and two memory instructions per cycle. The design was spread over six chips: an integer unit (with 16 KB instruction and 16 KB data caches), a floating-point unit, three fullfully-custom secondary cache tag RAMs (two for secondary cache accesses, one for bus snooping), and a cache controller ASIC. The design had two fully pipelined double precision multiply-add units, which could stream data from the 4 MB off-chip secondary cache. The R8000 powered SGI's [[SGI Challenge|POWER Challenge]] servers in the mid-1990s and later became available in the POWER Indigo2 workstation. Although its FPU performance fit scientific users quite well, its limited integer performance and high cost dampened appeal for most users. The R8000 was sold for only a year and remains fairly rare.

In 1995, the ''[[R10000]]'' was released. This processor was a single-chip design, ran at a higher clock frequency than the R8000, and had larger 32 KB primary instruction and data caches. It was also superscalar, but its major innovation was [[out-of-order execution]]. Even with one memory pipeline and simpler FPU, the vastly improved integer performance, lower price, and higher density made the R10000 preferable for most customers.