Compressed instruction set: Difference between revisions

Revision as of 11:38, 7 April 2022

Revision as of 01:34, 24 April 2022

Line 4:

The concept was originally introduced by [[Hitachi]] as a way to improve the [[code density]] of their [[SuperH]] [[RISC]] processor design as it moved from 16-bit to 32-bit instructions in the SH-5 version. The new design had two instruction sets, one giving access to the entire ISA of the new design, and a smaller 16-bit set known as SHcompact that allowed programs to run in smaller amounts of [[main memory]]. As the memory of even the smallest systems is now [[order-of-magnitude|orders of magnitude]] larger than the systems that spawned the concept, size is no longer the main concern. Today the advantage is that it reduces the number of accesses to main memory and thereby reduces energy use in [[mobile device]]s.

Hitachi's patents were licensed by [[Arm Ltd.]] for their processors, where it was known as "Thumb". Similar systems are found in MIPS16e and [[PowerPC]] VLE. The original patents have expired and the concept can be found in a number of modern designs, including the [[RISC-V]], which was designed from the outset to use it. The introduction of [[64-bit computing]] has led to the term no longer being as widely used; these processors generally use 32-bit instructions and are technically a form of compressed ISA, but as they are mostly modified versions of an older ISA from a 32-bit version of the same processor family; there is no real compression.

==Concept==