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Line 8: ==The classic five stage RISC pipeline== [[Image:Fivestagespipeline.png\|thumb\|400px\|Basic five-stage pipeline in a [[RISC]] machine (IF = [[Instruction fetch\|Instruction Fetch]], ID = Instruction Decode, EX = Execute, MEM = Memory access, WB = Register write back). The vertical axis sis successive instructions; the horizontal axis is time. So in the green column, the earliest instruction is in WB stage, and the latest instruction is undergoing instruction fetch.]] ===Instruction fetch===

Classic RISC pipeline: Difference between revisions