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====Differences between VMX and SPU====
The [VMX] technology is conceptually similar to the [[vector model]] provided by the [[SPU processors]], but there are many significant differences.
{| class="wikitable" style="margin: 1em auto 1em auto"
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! feature || VMX || SPU
|-
! [[word (computer science)|word]] size
| 32 bits || 32 bits
|-
! number of
| 32 <!-- p.28/333 --> || 128
<!-- p.34/333 also shows 32 GP and 32 FP regs, are these part of VMX? -->
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| 128 bit quadword <!-- p.28/333 --> || 128 bit quadword
|-
! [[integer]] formats
| 8, 16, 32 <!-- p.26/333 --> || 8, 16, 32 <!-- checked: there is no doubleword add or mul instr. -->
|-
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| big (default), little <!--p.44/333 --> || big endian
|-
! [[floating point (computer science)|floating point]] modes
| Java, non-Java || single precision, IEEE double
|-
! [[memory (computer science)|memory]] alignment
| quadword only || quadword only
|}
The VMX ''[[Java]] mode'' conforms to the [[Java Language Specification]] 1 subset of the default [[IEEE standard]], extended to include IEEE and C9X compliance where the Java standard falls silent. In a typical implementation, non-java mode converts [[denormal]] values to zero but java mode traps into an emulator when the [[processor (computer science)|processor]] encounters such a value. ''Non-Java mode'' might or might not be faster, might or might not be non-compliant.
Quadword (ie Four times a 32 bit word or 128 bits) alignment is on 16 Byte (128 bit) boundaries (ie the low four address bits are zero).
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