Depletion-load NMOS logic: Difference between revisions

Revision as of 21:38, 11 April 2022

Revision as of 03:39, 21 May 2022

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The inclusion of depletion-mode n-MOS transistors in the [[semiconductor manufacturing|manufacturing process]] demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of [[dopant]] in the load transistors channel region, in order to adjust their [[threshold voltage]]. This is normally performed using [[ion implantation]].

Although the [[CMOS]] process replaced most NMOS designs during the 1980s, some depletion-load nMOS designs are still produced, typically in parallel with newer CMOS counterparts. PneOne example of this is the [[Z80|Z84015]]<ref>''See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84015''.</ref> and Z84C15.<ref>''See http://www.zilog.com/index.php?option=com_product&Itemid=26&mode=showProductDetails&familyId=20&productId=Z84C15''.</ref>

==History and background==