Single-electron transistor: Difference between revisions

Revision as of 10:05, 7 August 2021

Revision as of 19:13, 12 July 2022

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[[File:SET schematic2.jpg|thumb|Schematic of a basic SET and its internal electrical components.]]

A '''single-electron transistor''' ('''SET''') is a sensitive electronic device based on the [[Coulomb blockade]] effect. In this device the electrons flow through a tunnel junction between source/drain to a [[quantum dot]] (conductive island). Moreover, the electrical potential of the island can be tuned by a third electrode, known as the gate, which is capacitively coupled to the island. The conductive island is sandwiched between two tunnel junctions,<ref>{{cite journal|last1=Mahapatra|first1=S.|last2=Vaish|first2=V.|last3=Wasshuber|first3=C.|last4=Banerjee|first4=K.|last5=Ionescu|first5=A.M.|title=Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design|journal=IEEE Transactions on Electron Devices|volume=51|issue=11|year=2004|pages=1772–1782|issn=0018-9383|doi=10.1109/TED.2004.837369|bibcode=2004ITED...51.1772M|s2cid=15373278}}</ref> which are modeled by a capacitor (<math>C_{\rm D}</math> and <math>C_{\rm S}</math>) and a resistor (<math>R_{\rm D}</math> and <math>R_{\rm S}</math>) in parallel.

<ref>{{cite journal|last1=Mahapatra|first1=S.|last2=Vaish|first2=V.|last3=Wasshuber|first3=C.|last4=Banerjee|first4=K.|last5=Ionescu|first5=A.M.|title=Analytical Modeling of Single Electron Transistor for Hybrid CMOS-SET Analog IC Design|journal=IEEE Transactions on Electron Devices|volume=51|issue=11|year=2004|pages=1772–1782|issn=0018-9383|doi=10.1109/TED.2004.837369|bibcode=2004ITED...51.1772M|s2cid=15373278}}</ref> which are modeled by a capacitor (<math>C_{\rm D}</math> and <math>C_{\rm S}</math>) and a resistor (<math>R_{\rm D}</math> and <math>R_{\rm S}</math>) in parallel.

== History ==

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=== Principle ===

[[File:Set schematic.svg|thumb|right|Schematic diagram of a single-electron transistor.]]

[[File:Single electron transistor.svg|thumb|right|Left to right: energy levels of source, island and drain in a single-electron transistor for the blocking state (upper part) and transmitting state (lower part).]]

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Various materials have successfully been tested when creating single-electron transistors. However, temperature is a huge factor limiting implementation in available electronical devices. Most of the metallic-based SETs only work at extremely low temperatures.

[[File:TySETimage.png|thumb|right|Single-electron transistor with [[niobium]] leads and [[aluminium]] island.]]

As mentioned in bullet 2 in the list above: the electrostatic charging energy must be greater than <math>k_{\rm B} T</math> to prevent thermal fluctuations affecting the [[Coulomb blockade]]. This in turn implies that the maximum allowed island capacitance is inversely proportional to the temperature, and needs to be below 1 aF to make the device operational at room temperature.

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=== CMOS compatibility ===

[[File:SETFET schematic.jpg|thumb|Hybrid SET-FETSET–FET circuit.]]

The level of the electrical current of the SET can be amplified enough to work with available [[CMOS]] technology by generating a hybrid SET-SET–[[field-effect transistor|FET]] device.<ref name="IonescuMahapatra2004">{{cite journal|last1=Ionescu|first1=A.M.|last2=Mahapatra|first2=S.|last3=Pott|first3=V.|title=Hybrid SETMOS Architecture With Coulomb Blockade Oscillations and High Current Drive|journal=IEEE Electron Device Letters|volume=25|issue=6|year=2004|pages=411–413|issn=0741-3106|doi=10.1109/LED.2004.828558|bibcode=2004IEDL...25..411I|s2cid=42715316}}</ref><ref name="AmatBausells2017">{{cite journal|last1=Amat|first1=Esteve|last2=Bausells|first2=Joan|last3=Perez-Murano|first3=Francesc|title=Exploring the Influence of Variability on Single-Electron Transistors Into SET-Based Circuits|journal=IEEE Transactions on Electron Devices|volume=64|issue=12|year=2017|pages=5172–5180|issn=0018-9383|doi=10.1109/TED.2017.2765003|bibcode=2017ITED...64.5172A|s2cid=22082690}}</ref>

The EU funded, in 2016, project IONS4SET (#688072)<ref>{{cite web|url=http://www.ions4set.eu|title=IONS4SET Website|access-date=2019-09-17}}</ref> looks for the manufacturability of SET-FETSET–FET circuits operative at room temperature. The main goal of this project is to design a SET-manufacturability process-flow for large-scale operations seeking to extend the use of the hybrid Set-CMOSSET–CMOS architectures. To assure room temperature operation, single dots of diameters below 5&nbsp;nm have to be fabricated and located between source and drain with tunnel distances of a few nanometers.<ref name="KlupfelBurenkov2016">{{cite book|last1=Klupfel|first1=F. J.|title=2016 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)|last2=Burenkov|first2=A.|last3=Lorenz|first3=J.|chapter=Simulation of silicon-dot-based single-electron memory devices|year=2016|pages=237–240|doi=10.1109/SISPAD.2016.7605191|isbn=978-1-5090-0818-6|s2cid=15721282}}</ref> Up to now there is no reliable process-flow to manufacture a hybrid SET-FETSET–FET circuit operative at room temperature. In this context, this EU project explores a more feasible way to manufacture the SET-FETSET–FET circuit by using pillar dimensions of approximately 10&nbsp;nm.<ref name="Xu2019">{{cite arXiv |eprint=1906.09975v2|last1=Xu|first1=Xiaomo|title=Morphology modification of Si nanopillars under ion irradiation at elevated temperatures: Plastic deformation and controlled thinning to 10 nm|last2=Heinig|first2=Karl-Heinz|last3=Möller|first3=Wolfhard|last4=Engelmann|first4=Hans-Jürgen|last5=Klingner|first5=Nico|last6=Gharbi|first6=Ahmed|last7=Tiron|first7=Raluca|author8=Johannes von Borany|last9=Hlawacek|first9=Gregor|class=physics.app-ph|year=2019}}</ref>

== See also ==