Talk:Microcode: Difference between revisions

Revision as of 08:21, 20 July 2022

Revision as of 08:52, 20 July 2022

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::: {{tqi|[…] Intel's document is not authoritative here […] }} See additional source above. The source is talking specifically about instructions-decoding microcode which simply map macro-instructions into a circuitry (e.g. ALU) that process data specified by macro-instructions. The microcode sits between decode & execute stages in the [[instruction cycle]]. It works like a microcontroller that treats MCU instructions as data and interprets it. I propose we keep my edit. Best.

:: <span style="font-weight: bold" >[[User:Alexander_Davronov|<span style="color:#a8a8a8;">AXO</span><span style="color:#000">NOV</span>]] [[User talk:Alexander_Davronov|(talk)]] [[Special:Contributions/Alexander_Davronov|⚑]]</span> 08:21, 20 July 2022 (UTC)

:::The source says:

:::{{quote| In a Complex Instruction Set (CISC) machine like x86, the stream of instructions read from memory are decoded into small operations known as micro-ops (μops).}}

:::In fully microcoded pre-P6 processors, the stream of instructions are read from memory by microcode and decoded by microcode, which then, based on the opcode, jumps to the microcode that executes the instruction in question. The instructions are not directly decoded into microinstructions/micro-ops. (The microcode that fetches and decodes the instructions, and the microcode that executes the instructions, may be executed by different processors, as per the VAX 8800 example and possibly other processors.)

:::In other processors, the instructions might be fetched and decoded by hardware, and that hardware may direct other hardware to execute some instructions and direct microcode to execute others, as per, for example, the [[Intel 80486]].

:::In the P6, instructions are fetched and decoded, probably by hardware. and translated on the fly into micro-ops that are scheduled for execution. This is the way all non-Atom x86 processors since the Pentium Pro work (I don't know whether the Atom processors work the same way or not).

:::If that's what the author of the document meant by "the stream of instructions read from memory are decoded into small operations known as micro-ops (μops)", then it's certainly true of all those x86 processors, and true (given IBM's use of the term "microop") of at least some z/Architecture processors, but it was ''not'' true of, for example, any of the IBM System/360 processors, probably not true of most if not all System/370 processors, not true of any microcoded PDP-11 processors not true of some if not all VAX processors and not, as far as I know, true of any Intel processors up to the 80386 (and possibly including the 80486 and original Pentium).

:::I.e., if that's what they meant, their statement does '''''NOT''''' apply to a large number of microcoded processors.

:::"The source is talking specifically about instructions-decoding microcode which simply map macro-instructions into a circuitry (e.g. ALU) that process data specified by macro-instructions. The microcode sits between decode & execute stages in the instruction cycle. It works like a microcontroller that treats MCU instructions as data and interprets it." is not at all clear:

:::I have ''no'' idea what it means to "map macro-instructions into a circuitry (e.g. ALU) that process data specified by macro-instructions."; which of the various types of processor I mention above does it refer, and how does it do so?

:::"It works like a microcontroller that treats MCU instructions as data and interprets it." is referring to the "In fully microcoded pre-P6 processors", ''not'' to the processors in which hardware reads macroinstructions and translates them to generated-on-the-fly micro-operations.

:::So I propose we ignore any edit that cannot distinguish between "microcode as simulator for an instruction set" (traditional microcode) and "micro-operations generated on the fly by the instruction decoder" (modern x86 and z/Architecture processors). [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 08:52, 20 July 2022 (UTC)