Content deleted Content added
Line 56:
=== Integrated memory controllers ===
Performance of typical MPU applications, such as [[packet processing]] and [[network control protocols]] (e.g. [[Signalling (telecommunications)|signalling]] and [[call control]]), is often sensitive to first-access [[memory latency]], i.e. the time taken to access memory that is not [[Cache|cached]] on chip, owing to high cache miss rate. This is sometimes more important than peak [[memory bandwidth]]. To achieve low first-access latency MPUs have integrated [[memory controllers]]. This is distinct from [[Intel]] and [[IBM]] general purpose processors that use separate memory controller devices adjacent to the processors and are more optimized for maximum bulk memory throughput.
=== Integrated streaming packet IO hardware ===
| |||