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=== Integrated streaming packet IO hardware ===
[[Embedded systems|Embedded]] packet processing and network control applications have heavy packet IO loads so many MPUs add streaming packet interface functions in on-chip [[hardware]] to [[offload]] these tasks from [[software]] on the processor cores. [[Layer-two]] [[protocol]] termination (e.g. [[Ethernet]] [[MAC]] layer) in hardware combined with packet input and output packet [[queues]] are typical. This is compared with general purpose processors that normally use memory address-space oriented interfaces such as [[PCI]], [[PCI-Express]] or [[Hypertransport]].
=== Packet processing acceleration hardware ===
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