512-bit computing: Difference between revisions

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==Hardware==
[[File:Sapphire Radeon R9 290X-front oblique PNr°0437.jpg|thumb|The AMD [[Radeon R9]] 290X (Sapphire OEM version pictured here) uses a 512 bit memory bus]]
The Intel [[Xeon Phi|Intel Xeon Phi]] has a [[vector processing unit]] with 512-bit vector registers, each one holding sixteen [[32-bit computing|32-bit]] elements or eight [[64-bit computing|64-bit]] elements, and a singleone instruction can operate on all these values in parallel. However, the Xeon Phi's vector processing unit does not operate on individual numbers that are 512 bits in lengthlong.<ref>{{cite web|url=https://software.intel.com/sites/default/files/managed/09/07/xeon-phi-coprocessor-system-software-developers-guide.pdf|title=Intel Xeon Phi Coprocessor System Software Developers Guide|publisher=[[Intel]]|date=March 2014|access-date=April 30, 2019}}</ref>
 
Some GPUs such as the [[AMDAdvanced Micro Devices]] (AMD) [[Radeon_HD_2000_seriesRadeon HD 2000 series#Radeon_HD_2900Radeon HD 2900|Radeon HD 2900XT]], the [[Nvidia]] GTX 280,<ref>{{cite web|url=http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-280/specifications |title=GTX 280 &#124;: Specifications |publisher=GeForce |access-date=2013-08-13}}</ref> GTX 285,<ref>{{cite web|url=http://www.geforce.com/hardware/desktop-gpus/geforce-gtx-285/specifications |title=GTX 285 &#124;: Specifications |publisher=GeForce |access-date=2013-08-13}}</ref> Quadro FX 5800<ref>{{cite web|url=http://www.nvidia.com/object/product_quadro_fx_5800_us.html |title=NVIDIA®Nvidia Quadro® FX 5800 provides professionals with visual supercomputing from their desktops delivering results that push visualization beyond traditional 3D |publisher=Nvidia.com |access-date=2013-08-13}}</ref> and several [[Nvidia Tesla]] products move data across a 512-bit memory bus. Then [[AMD Radeon Rx 200 Series#Radeon R9 290|AMD Radeon R9 290, R9 290X and 295X2]] followed.
 
[[AVX-512]] are 512-bit extensions to the 256-bit [[Advanced Vector Extensions]] SIMD instructions for x86 [[instruction set architecture]] proposed by Intel in July 2013, and released on 2016 with [[Xeon Phi#Knights Landing|Knights Landing]], and in 2017 on the HEDT and consumer server platform, with Skylake-X and [[Skylake (microarchitecture)#Skylake-SP (14 nm) Scalable Performance|Skylake-SP]] respectively.