Content deleted Content added
Typo |
link to Depletion_and_enhancement_modes...maybe these articles could be merged? or that one could become a subsection of MOSFET? |
||
Line 7:
In [[integrated circuit]]s, '''depletion-load NMOS''' is a form of digital [[logic family]] that uses only a single power supply voltage, unlike earlier [[NMOS logic|nMOS]] (n-type [[metal-oxide semiconductor]]) logic families that needed more than one different power supply voltage. Although manufacturing these integrated circuits required additional processing steps, improved switching speed and the elimination of the extra power supply made this logic family the preferred choice for many [[microprocessor]]s and other logic elements.
[[Depletion and enhancement modes|Depletion-mode]] n-type [[MOSFET]]s as load transistors allow single voltage operation and achieve greater speed than possible with pure enhancement-load devices. This is partly because the depletion-mode MOSFETs can be a better [[current source]] approximation than the simpler enhancement-mode transistor can, especially when no extra voltage is available (one of the reasons early pMOS and nMOS chips demanded several voltages).
The inclusion of depletion-mode n-MOS transistors in the [[semiconductor manufacturing|manufacturing process]] demanded additional manufacturing steps compared to the simpler enhancement-load circuits; this is because depletion-load devices are formed by increasing the amount of [[dopant]] in the load transistors channel region, in order to adjust their [[threshold voltage]]. This is normally performed using [[ion implantation]].
| |||