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{{Short description|Computer architecture bit width}}
{{primary sources|date=July 2013}}
{{n-bit|
There are currently no mainstream general-purpose [[CPU|processors]] built to operate on
==Representation==
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The Intel [[Xeon Phi]] has a [[vector processing unit]] with 512-bit vector registers, each one holding sixteen [[32-bit computing|32-bit]] elements or eight [[64-bit computing|64-bit]] elements, and one instruction can operate on all these values in parallel. However, the Xeon Phi's vector processing unit does not operate on individual numbers that are 512 bits long.<ref>{{cite web|url=https://software.intel.com/sites/default/files/managed/09/07/xeon-phi-coprocessor-system-software-developers-guide.pdf|title=Intel Xeon Phi Coprocessor System Software Developers Guide|publisher=[[Intel]]|date=March 2014|access-date=April 30, 2019}}</ref>
Some GPUs such as the [[Advanced Micro Devices]] (AMD) [[Radeon HD 2000 series#Radeon HD
[[AVX-512]] are 512-bit extensions to the 256-bit [[Advanced Vector Extensions]] SIMD instructions for x86 [[instruction set architecture]] proposed by Intel in July 2013, and released on 2016 with [[Xeon Phi#Knights Landing|Knights Landing]], and in 2017 on the HEDT and consumer server platform, with Skylake-X and [[Skylake (microarchitecture)#Skylake-SP (14 nm) Scalable Performance|Skylake-SP]] respectively.
==Software==
Many [[hash functions]], such as [[SHA-512]] and [[SHA3-512]], have a
==References==
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