Successive-approximation ADC: Difference between revisions

Revision as of 20:16, 8 August 2022

Revision as of 05:43, 1 October 2022

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{{No footnotes|date=March 2020}}

[[File:SA ADC block diagram.png|thumb|300px|Successive-approximation ADC block diagram showing digital-to-analog converter (DAC), end of conversion indicator (EOC), successive approximation register (SAR), sample and hold circuit (S/H), input voltage ({{math|''V''_INin}}) and reference voltage ({{math|''V''_REFref}})]]

A '''successive-approximation ADC''' is a type of [[analog-to-digital converter]] that converts a continuous [[analog waveform]] into a discrete [[Digital data|digital]] representation using a [[binary search]] through all possible [[Quantization (signal processing)|quantization]] levels before finally converging upon a digital output for each conversion.

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== Algorithm ==

The successive-approximation [[analog-to-digital converter]] circuit typically consists of four chief subcircuits:

# A [[sample-and-hold]] circuit to acquire the input [[voltage]] {{math|''V''_in}}.

# An analog voltage comparator that compares {{math|''V''_in}} to the output of the internal [[Digital-to-analog converter|DAC]] and outputs the result of the comparison to the successive-approximation [[Processor register|register]] (SAR).

# A successive-approximation register subcircuit designed to supply an approximate digital code of {{math|''V''_in}} to the internal DAC.

# An internal reference DAC that, for comparison with {{math|''V''_ref}}, supplies the [[comparator]] with an analog voltage equal to the digital code output of the {{math|SAR_in}}.

[[File:4-bit Successive Approximation DAC.gif|thumb|right|Animation of a 4-bit successive-approximation ADC]]

The successive approximation register is initialized so that the [[most significant bit]] (MSB) is equal to a [[Digital data|digital]] 1. This code is fed into the DAC, which then supplies the analog equivalent of this digital code {{math|(''V''_ref/2)}} into the comparator circuit for comparison with the sampled input voltage. If this analog voltage exceeds {{math|''V''_in}}, then the comparator causes the SAR to reset this bit; otherwise, the bit is left as 1. Then the next bit is set to 1 and the same test is done, continuing this [[Binary search algorithm|binary search]] until every bit in the SAR has been tested. The resulting code is the digital approximation of the sampled input voltage and is finally output by the SAR at the end of the conversion (EOC).

Mathematically, let {{math|1=''V''_in = ''xV''_ref}}, so {{math|''x''}} in {{math|[−1, 1]}} is the normalized input voltage. The objective is to approximately digitize {{math|''x''}} to an accuracy of {{frac|1/|2^''n''}}. The algorithm proceeds as follows:

# Initial approximation {{math|1=''x''₀ = 0}}.

# {{math|''i''^th}} approximation {{math|1=''x''_''i'' = ''x''_''i''−1 − ''s''(''x''_''i''−1 − ''x'')/2^''i''}}, where, {{math|''s''(''x'')}} is the [[signum function]] ({{math|1=sgn(''x'') = +1}} for {{math|''x'' ≥ 0}}, {{math|−1}} for {{math|''x'' < 0}}). It follows using mathematical induction that {{math|{{!}}''x''_''n'' − ''x''|{{!}} ≤ 1/2^''n''}}.

As shown in the above algorithm, a SAR ADC requires:

# An input voltage source {{math|''V''_in}}.

# A reference voltage source {{math|''V''_ref}} to normalize the input.

# A DAC to convert the {{math|''i''^th}} approximation {{math|''x''_''i''}} to a voltage.

# A comparator to perform the function {{math|''s''(''x''_''i'' − ''x'')}} by comparing the DAC's voltage with the input voltage.

# A register to store the output of the comparator and apply {{math|''x''_''i''−1 − ''s''(''x''_''i''−1 − ''x'')/2^''i''}}.

[[File:ADC animation 20.gif|thumb|alt=Successive approximation animation|Operation of successive-approximation ADC as input voltage falls from 5 to 0&nbsp;V. Iterations on the ''x'' axis. Approximation value on the ''y'' axis.|right]]

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===Variants===

;* Counter type ADC: The D to A converter can be easily turned around to provide the inverse function A to D conversion. The principle is to adjust the DAC's input code until the DAC's output comes within {{math|±{{frac|1|2}}}} LSB to the analog input which is to be converted to binary digital form.

;* Servo tracking ADC: It is an improved version of a counting ADC. The circuit consists of an up-down counter with the comparator controlling the direction of the count. The analog output of the DAC is compared with the analog input. If the input is greater than the DAC output signal, the output of the comparator goes high and the counter is caused to count up. The tracking ADC has the advantage of being simple. The disadvantage, however, is the time needed to stabilize as a new conversion value is directly proportional to the rate at which the analog signal changes.

==Charge-redistribution successive-approximation ADC==

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[[File:CAPadc.png|thumb|3 bits simulation of a capacitive ADC]]

# The capacitor array is completely discharged to the offset voltage of the comparator, {{math|''V''_OS}}. This step provides automatic offset cancellation (i.e. the offset voltage represents nothing but dead charge, which can't be juggled by the capacitors).

# All of the capacitors within the array are switched to the input signal {{math|''V''_in}}. The capacitors now have a charge equal to their respective capacitance times the input voltage minus the offset voltage upon each of them.

# The capacitors are then switched so that this charge is applied across the comparator input, creating a comparator input voltage equal to {{math|−''V''_in}}.

# The actual conversion process proceeds. First, the MSB capacitor is switched to {{math|''V''_ref}}, which corresponds to the full-scale range of the ADC. Due to the binary-weighting of the array, the MSB capacitor forms a 1:1 charge divider with the rest of the array. Thus, the input voltage to the comparator is now {{math|−''V''_in + {{frac|''V''_ref/|2}} }}. Subsequently, if {{math|''V''_in}} is greater than {{frac|''V''_ref/|2}}, then the comparator outputs a digital 1 as the MSB, otherwise it outputs a digital 0 as the MSB. Each capacitor is tested in the same manner until the comparator input voltage converges to the offset voltage, or at least as close as possible given the resolution of the DAC.

=== Use with non-ideal analog circuits ===

When implemented as an analog circuit – where the value of each successive bit is not perfectly {{math|2^''N''}} (e.g. 1.1, 2.12, 4.05, 8.01, etc.) – a successive-approximation approach might not output the ideal value because the binary search algorithm incorrectly removes what it believes to be half of the values the unknown input cannot be. Depending on the difference between actual and ideal performance, the maximal error can easily exceed several LSBs, especially as the error between the actual and ideal {{math|2^''N''}} becomes large for one or more bits. Since the actual input is unknown, it is therefore very important that accuracy of the analog circuit used to implement a SAR ADC be very close to the ideal {{math|2^''N''}} values; otherwise, it cannot guarantee a best match search.

== See also ==