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Aliyenimol (talk | contribs) Added concrete examples for application-specific instructin set processors, e.g. modular design of RISC-V ISA. |
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ASIPs can be used as an alternative of hardware accelerators for baseband signal processing<ref>Shahabuddin, Shahriar et al., "Design of a transport triggered vector processor for turbo decoding", Springer Journal of Analog Integrated Circuits and Signal Processing, March 2014. </ref> or video coding.<ref> Hautala, Ilkka, et al. "Programmable Low-Power Multicore Coprocessor Architecture for HEVC/H.265 In-Loop Filtering" in IEEE Transactions on Circuits and Systems for Video Technology, November 2014 </ref> Traditional hardware accelerators for these applications suffer from inflexibility. It is very difficult to reuse the hardware datapath with handwritten [[finite-state machine]]s (FSM). The retargetable compilers of ASIPs help the designer to update the program and reuse the datapath. Typically, the ASIP design is more or less dependent on the tool flow because designing a processor from scratch can be very complicated. One approach is to describe the processor using a high level language and then to automatically generate the ASIP's software toolset.<ref>Masarík, UML in design of ASIP, IFAC Proceedings Volumes 39(17):209-214, September 2006</ref> There are some commercial tools to design ASIPs from a high-level language, for example ASIP Designer from Synopsys or Studio from Codasip. There is an open source tool as well, TTA-based co-design environment (TCE).
== Examples ==
[[RISC-V|RISC-V Instruction Set Architecture]] (ISA) provides minimum base instruction sets that can be extended with additional application-specific instructions<ref>{{Cite book |last=Krste |first=CALIFORNIA UNIV BERKELEY DEPT OF ELECTRICAL ENGINEERING AND COMPUTER SCIENCES Waterman, Andrew Lee, Yunsup Patterson, David A Asanovi, |url=http://worldcat.org/oclc/913589579 |title=The RISC-V Instruction Set Manual. Volume 1: User-Level ISA, Version 2.0 |date=2014-05-06 |oclc=913589579}}</ref>. The base instruction sets provide simplified control flow, memory and arithmetic operations on registers. Its modular design allows the base instructions to be extended for standard application-specific operations such as integer multiplcation/division (M), single-precision floating point (F), or bit manipulation (B). For the non-standard instruction extensions, encoding space of the ISA is divided into three parts: ''standard, reserverd,'' and ''custom.'' The ''custom'' encoding space is used for vendor-specific extensions.
==See also==
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