Revision as of 22:45, 17 August 2022 edit Vincent Lefèvre (talk \| contribs) Extended confirmed users 5,222 edits →Representation: clarification (2^128 is not a 128-bit number, so let's make clear that this is the number of bytes with 128-bit addressing). ← Previous edit		Revision as of 12:18, 11 October 2022 edit undo 奧田95 (talk \| contribs) Extended confirmed users 2,792 edits →Hardware Tag: 2017 wikitext editor Next edit →
Line 19: CPUs feature [[Single instruction, multiple data\|SIMD]] instruction sets ([[Advanced Vector Extensions]] and the [[FMA instruction set]] etc.) where 256-bit vector [[processor register\|register]]s are used to store several smaller numbers, such as eight 32-bit [[floating-point]] numbers, and a single [[CPU instruction\|instruction]] can operate on all these values in parallel. However, these processors do not operate on individual numbers that are 256 binary digits in length, only their [[processor register\|registers]] have the size of 256-bits. Binary digits are found together in [[128-bit computing\|128-bit]] collections. Modern [[GPU]] chips ~~move~~may operate data across a 256-bit memory bus (or possibly a [[512-bit computing\|512-bit]] bus with [[High Bandwidth Memory\|HBM3]]<ref>{{Cite web\|first=Scharon \|last=Harding \|date=15 April 2021\|title=What Are HBM, HBM2 and HBM2E? A Basic Definition\|url=https://www.tomshardware.com/reviews/glossary-hbm-hbm2-high-bandwidth-memory-definition,5889.html\|access-date=2021-09-11\|website=Tom's Hardware\|language=en}}</ref>). The [[Transmeta Efficeon\|Efficeon]] processor was [[Transmeta]]'s second-generation 256-bit [[VLIW]] design which employed a software engine to convert code written for [[x86]] processors to the native instruction set of the chip.<ref>{{Cite web\|url=http://datasheets.chipdb.org/Transmeta/pdfs/brochures/efficeon_tm8300_processor.pdf\|title=Transmeta Efficeon TM8300 Processor\|publisher=[[Transmeta Corporation]]\|archive-url=https://web.archive.org/web/20190210132436/http://datasheets.chipdb.org/Transmeta/pdfs/brochures/efficeon_tm8300_processor.pdf\|archive-date=10 February 2019\|url-status=live}}</ref><ref>{{Cite web\|url=http://www.pcworld.com/article/101516/transmeta_unveils_plans_for_tm8000_processor.html\|title=Transmeta Unveils Plans for TM8000 Processor\|last=Williams\|first=Martyn\|date=29 May 2002\|website=[[PC World]]\|archive-url=https://web.archive.org/web/20100414160937/http://www.pcworld.com/article/101516/transmeta_unveils_plans_for_tm8000_processor.html\|archive-date=14 April 2010\|url-status=dead}}</ref>

256-bit computing: Difference between revisions