Inter-processor interrupt: Difference between revisions

Revision as of 03:09, 29 August 2022

Revision as of 16:16, 17 October 2022

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{{More references|date=December 2014}}

An '''inter-processor interrupt''' ('''IPI'''), also knowenknown as a ''shoulder tap'', is a special type of [[interrupt]] by which one processor may interrupt another processor in a [[multiprocessor]] system if the interrupting processor requires action from the other processor. Actions that might be requested include:

* flushes of [[memory management unit]] caches, such as [[translation lookaside buffer]]s, on other processors when memory mappings are changed by one processor;

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* Notify a processor that higher priority work is available.

* Notify a processor of work that cannot be done on all processors due to, e.g.,

** asymmetrcasymmetric access to I/O channels<ref>{{cite manual

| title = OS I/O Supervisor Logic - Release 21 - Program Number 360S-CI-505

| id = GY28-6616-9

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The [[OS/360 and successors#M65MP|M65MP]] option of [[OS/360 and successors|OS/360]] used the Direct Control feature of the [[IBM System/360|S/360]] to generate an interrupt on another processor; on [[IBM System/370|S/370]] and its successors, including [[z/Architecture]], the SIGNAL PROCESSOR instruction provides a more formalized interface. The documentation for some IBM operating systems refers to this as a shoulder tap.

On [[IBM PC compatible]] computers that use the [[Advanced Programmable Interrupt Controller]] (APIC), IPI signallingsignaling is often performed using the APIC. When a CPU wishes to send an interrupt to another CPU, it stores the [[interrupt vector]] and the identifier of the target's local APIC in the Interrupt Command Register (ICR) of its own local APIC. A message is then sent via the APIC bus to the target's local APIC, which therefore issues a corresponding interrupt to its own CPU.

== Examples ==