Gate array: Difference between revisions

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Early gate arrays were low performance and relatively large and expensive compared to state-of-the-art n-MOS technology then being used for custom chips. CMOS technology was being driven by very low power applications such as watch chips and battery operated portable instrumentation, not performance. They were also well under the performance of the existing dominant logic technology, transistor–transistor logic families. However, there were many niche applications where they were invaluable, particularly in low power, size reduction, portable and aerospace applications as well as time-to-market sensitive products. Even these small arrays could replace a board full of transistor–transistor logic gates if performance were not an issue. A common application was combining a number of smaller circuits that were supporting a larger LSI circuit on a board was affectionately known as "garbage collection". And the low cost of development and custom tooling made the technology available to the most modest budgets. Early gate arrays played a large part in the [[Citizens band radio#1970s popularity|CB craze in the 1970s]] as well as a vehicle for the introduction of other later mass-produced products such as modems and cell phones.
 
By the early 1980s gate arrays were starting to move out of their niche applications to the general market. Several factors in technology and markets were converging. Size and performance were increasing; automation was maturing; technology became "hot" when in 1981 IBM introduced its new flagship [[IBM 308X|3081]] mainframe with CPU comprising gate arrays,; they were used in a consumer product, the ZX81; and new entrants to the market increased visibility and credibility.<ref>{{cite book |first=Chris |last=Smith |title=The ZX Spectrum ULA: How To Design A Microcomputer |publisher=ZX Design and Media |oclc=751703922 |date=2010 |isbn=9780956507105 |pages= |url=http://www.zxdesign.info/book/insideULA.shtml}}</ref>
 
In 1981, [[Wilfred Corrigan]], Bill O'Meara Rob Walker and Mitchell "Mick" Bohn founded [[LSI Corporation|LSI Logic]].<ref>{{Cite web|url=http://www.computerhistory.org/collections/catalog/102746194|title=LSI Logic oral history panel {{!}} 102746194|website=Computer History Museum|access-date=2018-01-28}}</ref> Their initial intention was to commercialize emitter coupled logic gate arrays, but discovered the market was quickly moving towards CMOS. Instead they licensed CDI's silicon gate CMOS line as a second source. This product established them in the market while they developed their own proprietary 5 micron 2-layer metal line. This latter product line was the first commercial gate array product amenable to full automation. LSI developed a suite of proprietary development tools that allowed users to design their own chip from their own facility by remote login to LSI Logic's system.
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=== Decline ===
While the market boomed, profits for the industry were lacking. Semiconductors underwent a series of rolling [[List of recessions in the United States|recessions]] during the 1980s that created a boom-bust cycle. The 1980 and 1981-19821981–1982 general recessions were followed by high interest rates that curbed capital spending. This reduction played havoc on the semiconductor business that at the time was highly dependent on capital spending. Manufacturers desperate to keep their fab plants full and afford constant modernization in a fast moving industry became hyper-competitive. The many new entrants to the market drove gate array prices down to the marginal costs of the silicon manufacturers. Fabless companies such as LSI Logic and CDI survived on selling design services and computer time rather than on the production revenues.<ref name=":1" />
 
As of the early 21st century, the gate array market was a remnant of its former self, driven by the FPGA conversions done for cost or performance reasons. IMI moved out of gate arrays into mixed signal circuits and was later acquired by Cypress Semiconductor in 2001; CDI closed its doors in 1989; and LSI Logic abandoned the market in favor of standard products and was eventually acquired by Broadcom.<ref>{{Cite web|url=http://www.computerhistory.org/siliconengine/companies/|title=Companies|website=The Silicon Engine|publisher=Computer History Museum|access-date=2018-01-28}}</ref>
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The earliest gate arrays comprised [[bipolar transistors]], usually configured as high performance [[transistor–transistor logic]], [[emitter-coupled logic]] or [[current-mode logic]] logic configurations. [[CMOS]] (complementary [[metal-oxide-semiconductor]]) gate arrays were later developed and came to dominate the industry.
 
Gate array master slices with unfinished chips arrayed across a [[wafer (electronics)|wafer]] are usually prefabricated and stockpiled in large quantities regardless of customer orders. The design and fabrication according to the individual customer specifications can be finished in a shorter time than [[standard cell]] or [[full custom]] design. The gate array approach reduces the non recurring engineering [[Photomask|mask]] costs as fewer custom masks need to be produced. In addition, manufacturing test tooling lead time and costs are reduced - the same test fixtures can be used for all gate array products manufactured on the same [[Die (integrated circuit)|die]] size. Gate arrays were the predecessor of the more complex [[Structured ASIC platform|structured ASIC]]; unlike gate arrays, structured ASICs tend to include predefined or configurable memories and/or analog blocks.
 
An application circuit must be built on a gate array that has enough gates, wiring and I/O pins. Since requirements vary, gate arrays usually come in families, with larger members having more of all resources, but correspondingly more expensive. While the designer can fairly easily count how many gates and I/Os pins are needed, the number of routing tracks needed may vary considerably even among designs with the same amount of logic. (For example, a [[crossbar switch]] requires much more routing than a [[systolic array]] with the same gate count.) Since unused routing tracks increase the cost (and decrease the performance) of the part without providing any benefit, gate array manufacturers try to provide just enough tracks so that most designs that will fit in terms of gates and I/O pins can be routed. This is determined by estimates such as those derived from [[Rent's rule]] or by experiments with existing designs.
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Gate arrays were used widely in the [[home computer]] market in the United Kingdom in the early 1980s, including in the [[Sinclair ZX81]] and [[Sinclair Spectrum]], the [[BBC Micro]] and [[Acorn Electron]], and the [[Commodore Amiga]].
 
TheIn the 1980s the Forth [[RTX2010|Novix N4016]] and [[HP 3000]] Series 37 CPUs, both [[stack machine]]s were implemented by gate arrays as were some graphic terminal functions.<ref>{{cite journal |first=F.C. |last=Amerson |title=Simplicity in a Microcoded Computer Architecture |journal=Hewlett Packard Journal |volume=36 |issue=9 |pages=7–12 |date=September 1985 |doi= |url=https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1985-09.pdf |quote=The Series 37 CPU chip is a CMOS gate array using nearly 8000 gates.}}</ref><ref>{{cite journal |first1=J.E. |last1=Watkins |first2=P.A. |last2=Brown |first3=G. |last3=Szeman |first4=S.E. |last4=Carrie |title=Hardware Design of the HP 150 Personal Computer...it's really two products — a computer and a terminal |journal=Hewlett Packard Journal |volume=35 |issue=8 |pages=25–30 |date=August 1984 |url=https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1984-08.pdf |quote=To reduce the IC count on the video card, a PLA (programmable logic array) and a TTL gate array are used. The gate array implements most of the circuitry of the graphics controller section, including control of the RAM. Compared to discrete circuitry, the gate array consumes one fifth the space, one fourth the power, and one half the cost.}}</ref> Some supporting hardware in at least 1990s [[VAX_7000_and_VAX_10000|DEC]] and [[HP_9000#S/X-class|HP]] servers was implemented by gate arrays.<ref>{{cite journal |last1=Allison |first1=B.R. |last2=Van Ingen |first2=C. |title=Technical description of the DEC 7000 and DEC 10000 AXP family |journal=Digital Technical Journal |volume=4 |issue=4 |pages=100– |date=1992 |doi= |url=https://www.linux-mips.org/pub/linux/mips/people/macro/DEC/DTJ/DTJ806/DTJ806PF.PDF |quote=All modules utilize LSI Logic LCA100K series gate arrays for the system bus interface and for on-board logic functions. The LSI Logic LCA100K features up to 235K two-input NAND gates. All modules use the same custom I/O driver circuit within their respective gate arrays to drive and receive the system bus. A custom 419-pin pin grid array (PGA) package was developed to house all bus interface gate arrays. ... A minimal DEC 7000 system includes 430,000 gates of logic contained in gate arrays, whereas a minimal [[VAX_6000#VAX_6000_Model_2x0|VAX 6000 Model 200]] includes 94,000 gates.}}</ref><ref>{{cite journal |last1=Bening |first1=L.C. |last2=Brewer |first2=T.M. |last3=Foster |first3=H.D. |last4=Quigley |first4=J.S. |last5=Sussman |first5=R.A. |last6=Vogel |first6=P.F. |last7=Wells |first7=A.W. |title=Physical Design of 0.35-μm Gate Arrays for Symmetric Multiprocessing Servers |journal=Hewlett-Packard Journal |volume=48 |issue=2 |pages=95–103 |date=1997 |doi= |url=httphttps://shiftleft.com/mirrors/www.hpl.hp.com/hpjournal/97aprpdfs/apr97a16IssuePDFs/1997-04.pdf |quote=The PA 8000s will initially run at 180 MHz, with the rest of the system running at 120 MHz. Except for the [[PA-8000|PA 8000]] and associated SRAMs and DRAMs, the bulk of the system logic is implemented in Fujitsu CG61 0.35-μm gate arrays, as shown in Table I. (Processor Interface, Crossbar, Memory Interface, Node-to-Node Interface) One additional gate array is implemented in the much less expensive CG51 0.5-μm process. (I/O Interface)}}</ref>
 
== References ==