Pass transistor logic: Difference between revisions

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In [[electronics]], '''pass transistor logic''' (PTL) describes several [[logic family|logic families]] used in the design of [[integrated circuit]]s. It reduces the count of transistors used to make different [[logic gate]]s, by eliminating redundant transistors. Transistors are used as switches to pass [[logic level]]s between nodes of a circuit, instead of as switches connected directly to supply voltages.<ref>{{cite book |first1=Jaume |last1=Segura, |first2=Charles F. |last2=Hawkins ''|title=CMOS electronics: how it works, how it fails'', |publisher=Wiley-IEEE, |date=2004 {{ISBN |isbn=0-471-47669-2}}, page |pages=132 |url=}}</ref> This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage. Each transistor in series is less saturated at its output than at its input.<ref>{{cite book |first=Clive |last=Maxfield ''|title=Bebop to the boolean boogie: an unconventional guide to electronics'' |publisher=Newnes, |date=2008 {{ISBN|isbn=978-1-85617-507-34 |pages=423–6 |url=}}, pp. 423-426</ref> If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional [[CMOS logic]] switches transistors so the output connects to one of the power supply rails (resembling an [[open collector]] scheme), so logic voltage levels in a sequential chain do not decrease.

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XOR using pass-transistor logic

rather than simple gates.<ref>

{{cite web |first=Ken |last=Shirriff.

[ |url=http://www.righto.com/2013/09/understanding-z-80-processor-one-gate.html "|title=Reverse-engineering the Z-80: the silicon for two interesting gates explained"]. |date=2013}}

2013.

</ref>

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Some authors use the term "complementary pass transistor logic" to indicate a style of implementing logic gates that uses [[transmission gate]]s composed of both NMOS and PMOS pass transistors.<ref>

{{cite book |first=Gary K. |last=Yeap |title=Practical Low Power Digital VLSI Design |publisher=Springer |orig-year=1998 |date=2012 |isbn=978-1-4615-6065-4 |pages=197 |url=https://books.google.com/books?id=sXTdBwAAQBAJ}}

Gary K. Yeap.

[https://books.google.com/books?id=sXTdBwAAQBAJ "Practical Low Power Digital VLSI Design"].

2012.

p. 197.

</ref>

Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates where each gate consists of a NMOS-only pass transistor network, followed by a CMOS output inverter.<ref>

{{cite book |first=Vojin G. |last=Oklobdzija |title=Digital Design and Fabrication |publisher= |date= 19 December 2017|isbn= 9780849386046|pages=2–39 |url=https://books.google.com/books?id=VOnyWUUUj04C}}

Vojin G. Oklobdzija.

[https://books.google.com/books?id=VOnyWUUUj04C "Digital Design and Fabrication"].

p. 2-39.

</ref><ref name="IEEE_1990"/><ref name="ULVD_2015"/>

Other authors use the term "complementary pass transistor logic" (CPL) to indicate a style of implementing logic gates using dual-rail encoding. Every CPL gate has two output wires, both the positive signal and the complementary signal, eliminating the need for inverters.<ref>

{{cite book |editor-first=Wai-Kai |editor-last=Chen |title=Logic Design |publisher=CRC Press |___location= |date=2003 |isbn=978-0-203-01015-0 |pages=15–7 |url=https://books.google.com/books?id=X0a3BgAAQBAJ |oclc=1029500642}}

Wai-Kai Chen.

[https://books.google.com/books?id=X0a3BgAAQBAJ "Logic Design"].

2003.

p. 15-7.

</ref><ref>

{{cite book |editor-first=Vojin G. |editor-last=Oklobdzija |title=The Computer Engineering Handbook |publisher=Taylor & Francis |___location= |date=2001 |isbn=978-0-8493-0885-7 |pages=2-23–2-24 |url=https://books.google.com/books?id=38Aj3CjHgc8C}}

Vojin G. Oklobdzija.

[https://books.google.com/books?id=38Aj3CjHgc8C "The Computer Engineering Handbook"].

2001.

p. 2-23 to 2-24.

</ref><ref>

{{cite book |first=Ajit |last=Pal |title=Low-Power VLSI Circuits and Systems |publisher=Springer |date=2014 |isbn=978-81-322-1937-8 |pages=109–110 |url=https://books.google.com/books?id=0I1xBQAAQBAJ |chapter=5.2.3 Pass-Transistor Logic Families |chapter-url={{GBurl|0I1xBQAAQBAJ|p=109}}}}

Ajit Pal.

[https://books.google.com/books?id=0I1xBQAAQBAJ "Low-Power VLSI Circuits and Systems"].

p. 109 to 110.

</ref>

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==Other forms==

Static and dynamic types of pass transistor logic exist, with differing properties with respect to speed, power and low-voltage operation.<ref>{{cite book |first=Cornelius T. |last=Leondes ''|title=Digital signal processing systems: implementation techniques'' |publisher=Elsevier, |date=1995 {{ISBN|isbn=0-12-012768-7}} page |pages=2 |url=}}</ref> As integrated circuit supply voltages decrease, the disadvantages of pass transistor logic become more significant; the threshold voltage of transistors becomes large compared to the supply voltage, severely limiting the number of sequential stages. Because complementary inputs are often required to control pass transistors, additional logic stages are required.

==References==

{{Reflist|refs=

<ref name="IEEE_1990">{{cite journal |title=A 3.8-ns CMOS 16x16-b multiplier using complementary pass-transistor logic |author-last1=Yano |author-first1=Kuniaki |author-last2=Yamanaka |author-first2=Toshiaki Yamanaka |author-last3=Nishida |author-first3=Takeshi |author-last4=Saito |author-first4=Mitsuo |author-last5=Shimohigashi |author-first5=Katsuhiro |author-last6=Shimizu |author-first6=Atsushi |date=1990 |journal=[[IEEE Journal of Solid-State Circuits]] |volume=25 |issue=2 |pages=388–395 |doi=10.1109/4.52161|bibcode=1990IJSSC..25..388Y }}</ref>

<ref name="ULVD_2015">{{cite book |title=Ultra-Low-Voltage Design of Energy-Efficient Digital Circuits |author-first1=Nele |author-last1=Reynders |author-first2=Wim |author-last2=Dehaene |series=Analog Circuits And Signal Processing (ACSP) |date=2015 |edition=1 |___location=Heverlee, Belgium |publisher=[[Springer International Publishing AG Switzerland]] |publication-place=Cham, Switzerland |isbn=978-3-319-16135-8 |issn=1872-082X |doi=10.1007/978-3-319-16136-5 |lccn=2015935431}}</ref>

}}

==Further reading==

*{{cite book |last1=Weste and |last2=Harris, |title=CMOS VLSI Design, Third|year=2005 Edition|publisher= ({{ISBN|edition=3rd |isbn=0-321-14901-7}}; {{ISBN|0-321-26977-2pages= |url=}} (international edition))

*{{cite book |first1=Douglas A. |last1=Pucknell and |first2=Kamran |last2=Eshraghian, |title=Basic VLSI Design, Third|year=1994 Edition|publisher= ({{ISBN|edition=3rd |isbn=978-81-203-0986-9}} (Indian|pages= Edition))|url=}}

{{Logic Families}}