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==Flynn's taxonomy==
{{Main|Flynn's taxonomy}}
Typically, latency oriented processor architectures execute a single task operating on a single data stream, and so they are [[Single instruction, single data|SISD]] under Flynn's taxonomy. Latency oriented processor architectures might also include [[Single instruction, multiple data|SIMD]] instruction set extensions such as Intel [[MMX (instruction set)|MMX]] and [[Streaming SIMD Extensions|SSE]]; even though these extensions operate on large data sets, their primary goal is to reduce overall latency.<ref name=YanSohilin2016/>
==Implementation techniques==
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