Multi-level cell: Difference between revisions

Content deleted Content added
Quad-level cell: fix serious misunderstanding "rewriting history" from revision 940444583 + citation needed tag
AnomieBOT (talk | contribs)
m Dating maintenance tags: {{Cn}}
Line 54:
== Quad-level cell ==
[[File:Samsung 870 QVO 8TB SATA 2,5 Zoll Internes Solid State Drive (SSD) (MZ-77Q8T0BW) 20211008 SSD023 corr.png|thumb|right|alt=A grey SSD with the text Samsung Solid State Drive"|The Samsung 870 QVO: A QLC SSD with 8 TB storage]]
Memory that stores 4 bits per cell is commonly referred to as '''quad-level cell''' ('''QLC'''), following the convention set by '''TLC'''. Prior to its invention, the term "QLC" was synonymous with MLC in referring to cells that can have 4 voltage states, i.e. ones that store 2 bits per cell – what is now unambiguously referred to as DLC.{{cn|date=December 2022}}
 
In 2009, Toshiba and [[SanDisk]] introduced [[NAND flash]] memory chips with quad-level cells, storing 4&nbsp;bits per cell and holding a capacity of 64{{nbsp}}Gbit.<ref name="toshiba2009"/><ref>{{cite news |title=SanDisk ships world's first memory cards with 64 gigabit X4 NAND flash |url=https://www.slashgear.com/sandisk-ships-worlds-first-memory-cards-with-64-gigabit-x4-nand-flash-1360217/ |access-date=20 June 2019 |work=SlashGear |date=13 October 2009}}</ref>