Logic simulation: Difference between revisions

Revision as of 00:49, 3 January 2023

Revision as of 00:58, 3 January 2023

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A prospective way to accelerate logic simulation is using [[distributed computing|distributed]] and [[parallel computing|parallel]] computations.<ref>Software system for distributed [[Event-driven programming|event-driven]] logic simulation. Ladyzhensky Y.V., Popoff Y.V. Proceedings of IEEE East-West Design & Test Workshop(EWDTW'05). IEEE EWDTW, 2005, p.119-122 {{ISBN|966-659-113-8}}</ref>

To help gauge the thoroughness of a simulation, tools exist for assessing [[code coverage]], functional coverage and logic coverage tools.<ref>{{cite conference

|title=Practical code coverage for Verilog

|author=Wang, Tsu-Hua and Tan, Chong Guan

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|publisher=IEEE

|url=https://ieeexplore.ieee.org/abstract/document/512503 }}</ref>

functional coverage, finite state machine (FSM) coverage, and many other metrics.<ref>{{cite conference

|title=Coverage analysis techniques for HDL design validation

|author=Jou, Jing-Yang and Liu, Chien-Nan Jimmy

|conference=Asia Pacific CHip Design Languages

|pages=48-55,

|year=1999

|url=https://www.researchgate.net/profile/Chien-Nan-Liu/publication/266883269_Coverage_Analysis_Techniques_for_HDL_Design_Validation/links/54a566420cf256bf8bb4cf95/Coverage-Analysis-Techniques-for-HDL-Design-Validation.pdf}}</ref>

== Event simulation versus cycle simulation ==