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Undid revision 1130845328 by CoolingGibbon (talk)As the lede says, this article is about more than "instruction set architecture." Talk if there is any objection rather than revert |
John Sauter (talk | contribs) Big-endian -> big-endian in cross references Tag: Reverted |
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* 64-bit processor status register (PSW), which includes a 24-bit [[Program counter|instruction address]]
* 24-bit (16 MB) byte-addressable memory space
* [[big-endian|Big-endian]] byte/word order
* A ''standard instruction set'', including fixed-point binary arithmetic and logical instructions, present on all System/360 models (except the [[IBM System/360 Model 20|Model 20]], see below).
** A ''commercial instruction set'', adding decimal arithmetic instructions, is optional on some models, as is a ''scientific instruction set'', which adds floating-point instructions. The ''universal instruction set'' includes all of the above plus the storage protection instructions and is standard for some models.
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