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{{short description|Type of interrupt signal sent between computer processors}}
{{More references|date=December 2014}}
* flushes of [[memory management unit]] caches, such as [[translation lookaside buffer]]s, on other processors when memory mappings are changed by one processor;
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* Notify a processor that higher priority work is available.
* Notify a processor of work that cannot be done on all processors due to, e.g.,
** asymmetric access to [[I/O
| title = OS I/O Supervisor Logic - Release 21 - Program Number 360S-CI-505
| id = GY28-6616-9
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