Multi-level cell: Difference between revisions

Revision as of 22:14, 29 December 2022

Revision as of 21:25, 23 January 2023

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MLC flash may have a lifetime of about 1,000 to 10,000 program/erase cycles. This typically necessitates the use of a [[flash file system]], which is designed around the limitations of flash memory, such as using [[wear leveling]] to extend the useful lifetime of the flash device.

The [[Intel 8087]] used two-bits-per-cell technology for its [[microcode]] [[ROM]],<ref>{{Cite web |title=Two bits per transistor: high-density ROM in Intel's 8087 floating point chip |url=http://www.righto.com/2018/09/two-bits-per-transistor-high-density.html |access-date=2022-05-18}}</ref> and in 1980 was one of the first devices on the market to use multi-level ROM cells.<ref>"Four-state cell called density key" article by J. Robert Lineback. "Electronics" magazine. 1982 June 30.</ref><ref>P. Glenn Gulak. [https://web.archive.org/web/20180528133902/https://pdfs.semanticscholar.org/a3c1/cbc425c7987fe2307b48e0ff96f2c2c1b038.pdf "A Review of Multiple-Valued Memory Technology"].</ref> [[Intel]] later demonstrated 2-bit multi-level cell (MLC) [[NOR flash]] in 1997.<ref name="Smithsonian">{{cite web |title=The Flash Memory Market |url=http://smithsonianchips.si.edu/ice/cd/MEMORY97/SEC05.PDF |website=Integrated Circuit Engineering Corporation |publisher=[[Smithsonian Institution]] |year=1997 |access-date=16 October 2019}}</ref> [[NEC]] demonstrated quad-level cells in 1996, with a 64{{nbsp}}[[Mebibit|Mbit]] [[flash memory]] chip storing 2&nbsp;bits per cell. In 1997, NEC demonstrated a [[dynamic random-access memory]] (DRAM) chip with quad-level cells, holding a capacity of 4{{nbsp}}Gbit. [[STMicroelectronics]] also demonstrated quad-level cells in 2000, with a 64{{nbsp}}Mbit [[NOR flash]] memory chip.<ref name="stol">{{cite web |title=Memory |url=http://maltiel-consulting.com/Semiconductor_technology_memory.html |website=STOL (Semiconductor Technology Online) |access-date=25 June 2019}}</ref>

MLC is used to refer to cells that store 2&nbsp;bits per cell, using 4 charge values or levels. A 2-bit MLC has a single charge level assigned to every possible combination of ones and zeros, as follows: When close to 25% full, the cell represents a binary value of 11; when close to 50%, the cell represents a 01; when close to 75%, the cell represents a 00; and when close to 100%, the cell represents a 10. Once again, there is a region of uncertainty (read margin) between values, at which the data stored in the cell cannot be precisely read.<ref>{{cite web |url=https://www.enterprisestorageforum.com/storage-hardware/slc-vs-mlc-vs-tlc-nand-flash.html |author=Pedro Hernandez |title=SLC vs MLC vs TLC NAND Flash |website=Enterprise Storage Forum |date=June 29, 2018}}</ref><ref name="anandtech">{{Cite web |url=https://www.anandtech.com/show/4902/intel-ssd-710-200gb-review/2 |title = The Intel SSD 710 (200GB) Review}}</ref>