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== Multi-level cell ==
The primary benefit of MLC flash memory is its lower cost per unit of storage due to the higher data density, and memory-reading software can compensate for a larger [[bit error rate]].<ref>[http://www.micron.com/products/nand/mlc-webinar.aspx Micron's MLC NAND Flash Webinar]. {{webarchive|url=https://web.archive.org/web/20070722200149/http://www.micron.com/products/nand/mlc-webinar.aspx |date=2007-07-22 }}.</ref> The higher error rate necessitates an [[error-correcting code]] (ECC) that can correct multiple bit errors; for example, the [[SandForce]] SF-2500 flash controller can correct up to 55 bits per 512-byte sector with an unrecoverable read error rate of less than one sector per 10<sup>17</sup> bits read.<ref>{{Cite web |title=SandForce® SF2600 and SF2500 Enterprise datasheet |url=https://www.seagate.com/www-content/product-content/lsi-fam/enterprise-flash-controller/en-us/docs/enterprise-fsp-sf-2500-ds1828-1-1409us.pdf |access-date=2023-02-11 |website=[[Seagate Technology|Seagate]]}}</ref> The most commonly used algorithm is Bose–Chaudhuri–Hocquenghem ([[BCH code]]).<ref>{{Cite web |last=EETimes |date=2013-08-27 |title=A Tour of the Basics of Embedded NAND Flash Options |url=https://www.eetimes.com/a-tour-of-the-basics-of-embedded-nand-flash-options/ |access-date=2023-02-11 |website=EE Times}}</ref> Other drawbacks of MLC NAND are lower write speeds, lower number of program/erase cycles and higher power consumption compared to SLC flash memory.
Read speeds can also be lower for MLC NAND than SLC due to the need to read the same data at a second threshold voltage to help resolve errors. TLC and QLC devices may need to read the same data up to 4 and 8 times respectively to obtain values that are correctable by ECC.<ref>{{cite journal |last1=Peleato |display-authors=etal |title=Adaptive Read Thresholds for NAND Flash |journal=IEEE Transactions on Communications |date=Sep 2015 |volume=63 |issue=9 |pages=3069–3081 |doi=10.1109/TCOMM.2015.2453413 |s2cid=14159361|arxiv=2202.05661 }}</ref>
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