Gate array: Difference between revisions

Revision as of 11:23, 4 February 2023

Revision as of 15:52, 13 February 2023

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== Uses ==

{{expand section|date=June 2022}}

Gate arrays were used widely in the [[home computer]] markets in the United Kingdom in the early to mid 1980s, including in the [[Sinclair ZX81]] and, [[SinclairZX Spectrum]], the [[BBC Micro]] and, [[Acorn Electron]], and the [[Commodore Amiga]].

In the 1980s the Forth [[RTX2010|Novix N4016]] and [[HP 3000]] Series 37 CPUs, both [[stack machine]]s were implemented by gate arrays as were some graphic terminal functions.<ref>{{cite journal |first=F.C. |last=Amerson |title=Simplicity in a Microcoded Computer Architecture |journal=Hewlett Packard Journal |volume=36 |issue=9 |pages=7–12 |date=September 1985 |url=https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1985-09.pdf |quote=The Series 37 CPU chip is a CMOS gate array using nearly 8000 gates.}}</ref><ref>{{cite journal |first1=J.E. |last1=Watkins |first2=P.A. |last2=Brown |first3=G. |last3=Szeman |first4=S.E. |last4=Carrie |title=Hardware Design of the HP 150 Personal Computer...it's really two products — a computer and a terminal |journal=Hewlett Packard Journal |volume=35 |issue=8 |pages=25–30 |date=August 1984 |url=https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1984-08.pdf |quote=To reduce the IC count on the video card, a PLA (programmable logic array) and a TTL gate array are used. The gate array implements most of the circuitry of the graphics controller section, including control of the RAM. Compared to discrete circuitry, the gate array consumes one fifth the space, one fourth the power, and one half the cost.}}</ref> Some supporting hardware in at least 1990s [[VAX_7000_and_VAX_10000|DEC]] and [[HP_9000#S/X-class|HP]] servers was implemented by gate arrays.<ref>{{cite journal |last1=Allison |first1=B.R. |last2=Van Ingen |first2=C. |title=Technical description of the DEC 7000 and DEC 10000 AXP family |journal=Digital Technical Journal |volume=4 |issue=4 |pages=100– |date=1992 |doi= |url=https://www.linux-mips.org/pub/linux/mips/people/macro/DEC/DTJ/DTJ806/DTJ806PF.PDF |quote=All modules utilize LSI Logic LCA100K series gate arrays for the system bus interface and for on-board logic functions. The LSI Logic LCA100K features up to 235K two-input NAND gates. All modules use the same custom I/O driver circuit within their respective gate arrays to drive and receive the system bus. A custom 419-pin pin grid array (PGA) package was developed to house all bus interface gate arrays. ... A minimal DEC 7000 system includes 430,000 gates of logic contained in gate arrays, whereas a minimal [[VAX_6000#VAX_6000_Model_2x0|VAX 6000 Model 200]] includes 94,000 gates.}}</ref><ref>{{cite journal |last1=Bening |first1=L.C. |last2=Brewer |first2=T.M. |last3=Foster |first3=H.D. |last4=Quigley |first4=J.S. |last5=Sussman |first5=R.A. |last6=Vogel |first6=P.F. |last7=Wells |first7=A.W. |title=Physical Design of 0.35-μm Gate Arrays for Symmetric Multiprocessing Servers |journal=Hewlett-Packard Journal |volume=48 |issue=2 |pages=95–103 |date=1997 |doi= |url=https://www.hpl.hp.com/hpjournal/pdfs/IssuePDFs/1997-04.pdf |quote=The PA 8000s will initially run at 180 MHz, with the rest of the system running at 120 MHz. Except for the [[PA-8000|PA 8000]] and associated SRAMs and DRAMs, the bulk of the system logic is implemented in Fujitsu CG61 0.35-μm gate arrays, as shown in Table I. (Processor Interface, Crossbar, Memory Interface, Node-to-Node Interface) One additional gate array is implemented in the much less expensive CG51 0.5-μm process. (I/O Interface)}}</ref>