Logic simulation: Difference between revisions

Revision as of 18:13, 4 January 2023

Revision as of 15:52, 19 February 2023

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==Use in verification==

Logic simulation may be used as part of the [[Verification and validation|verification]] process in designing hardware.<ref name="ResearchGate">{{cite journal |last1=Bombieri |first1=Nicola |last2=Fummi |first2=Franco |last3=Pravadelli |first3=Graziano |title=Hardware Design and Simulation for Verification |journal=Lecture Notes in Computer Science |date=May 2006 |pages=1–29 |url=https://www.researchgate.net/publication/221224340_Hardware_Design_and_Simulation_for_Verification221224340}}</ref>

Simulations have the advantage of providing a familiar look and feel to the user in that it is constructed from the same language and symbols used in design. By allowing the user to interact directly with the design, simulation is a natural way for the designer to get feedback on their design.

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|year=1995

|publisher=IEEE

|url=https://ieeexplore.ieee.org/abstract/document/512503 }}</ref>

functional coverage, finite state machine (FSM) coverage, and many other metrics.<ref>{{cite conference

|title=Coverage analysis techniques for HDL design validation

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|pages=48–55

|year=1999

|url=https://www.researchgate.net/profile/Chien-Nan-Liu/publication/266883269_Coverage_Analysis_Techniques_for_HDL_Design_Validation/links/54a566420cf256bf8bb4cf95/Coverage-Analysis-Techniques-for-HDL-Design-Validation.pdf266883269}}</ref>

== Event simulation versus cycle simulation ==