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With this information about what the device looks like, the device simulator models the physical processes taking place in the device to determine its electrical behavior in a variety of circumstances: DC current–voltage behavior, transient behavior (both large-signal and small-signal), dependence on device layout (long and narrow versus short and wide, or interdigitated versus rectangular, or isolated versus proximate to other devices). These simulations tell the device designer whether the device process will produce devices with the electrical behavior needed by the circuit designer, and is used to inform the process designer about any necessary process improvements. Once the process gets close to manufacture, the predicted device characteristics are compared with measurement on test devices to check that the process and device models are working adequately.
Although long ago the device behavior modeled in this way was very simple{{spaced en dash}} mainly drift plus diffusion in simple geometries{{spaced en dash}} today many more processes must be modeled at a microscopic level; for example, leakage currents<ref name=":0">{{Cite patent|number=WO2000077533A3|title=Semiconductor device simulation method and simulator|gdate=2001-04-26|invent1=Lui|inventor1-first=Basil|url=https://patents.google.com/patent/WO2000077533A3/en?inventor=Basil+Lui}}</ref> in junctions and oxides, complex transport of carriers including [[velocity saturation]] and ballistic transport, quantum mechanical effects, use of multiple materials (for example, [[SiGe#SiGe Transistors|Si-SiGe]] devices, and stacks of different [[high-κ dielectric|dielectrics]]) and even the statistical effects due to the probabilistic nature of ion placement and carrier transport inside the device. Several times a year the technology changes and simulations have to be repeated. The models may require change to reflect new physical effects, or to provide greater accuracy. The maintenance and improvement of these models is a business in itself.
These models are very computer intensive, involving detailed spatial and temporal solutions of coupled partial differential equations on three-dimensional grids inside the device.<ref name=Jacoboni>
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====Physical models====
: These are [[Semiconductor device modeling|models based upon device physics]], based upon approximate modeling of physical phenomena within a transistor<ref name=":0" /><ref>{{Cite journal |last=Lui |first=Basil |last2=Migliorato |first2=P |date=1997-04-01 |title=A new generation-recombination model for device simulation including the Poole-Frenkel effect and phonon-assisted tunnelling |url=https://www.sciencedirect.com/science/article/pii/S0038110196001487 |journal=Solid-State Electronics |language=en |volume=41 |issue=4 |pages=575–583 |doi=10.1016/S0038-1101(96)00148-7 |issn=0038-1101}}</ref>. Parameters<ref>{{Cite journal |last=Lui |first=Basil |last2=Tam |first2=S. W. B. |last3=Migliorato |first3=P. |date=1998 |title=A Polysilicon Tft Parameter Extractor |url=https://www.cambridge.org/core/journals/mrs-online-proceedings-library-archive/article/abs/polysilicon-tft-parameter-extractor/AFB82CB806F1140E9249C5FA90285B66 |journal=MRS Online Proceedings Library (OPL) |language=en |volume=507 |pages=365 |doi=10.1557/PROC-507-365 |issn=0272-9172}}</ref><ref>{{Cite journal |last=Kimura |first=Mutsumi |last2=Nozawa |first2=Ryoichi |last3=Inoue |first3=Satoshi |last4=Shimoda |first4=Tatsuya |last5=Lui |first5=Basil |last6=Tam |first6=Simon Wing-Bun |last7=Migliorato |first7=Piero |date=2001-09-01 |title=Extraction of Trap States at the Oxide-Silicon Interface and Grain Boundary for Polycrystalline Silicon Thin-Film Transistors |url=https://iopscience.iop.org/article/10.1143/JJAP.40.5227/meta |journal=Japanese Journal of Applied Physics |language=en |volume=40 |issue=9R |pages=5227 |doi=10.1143/JJAP.40.5227 |issn=1347-4065}}</ref> within these models are based upon physical properties such as oxide thicknesses, substrate doping concentrations, carrier mobility, etc<ref>{{Cite journal |last=Lui |first=Basil |last2=Tam |first2=S. W.-B. |last3=Migliorato |first3=P. |last4=Shimoda |first4=T. |date=2001-06-01 |title=Method for the determination of bulk and interface density of states in thin-film transistors |url=https://aip.scitation.org/doi/abs/10.1063/1.1361244 |journal=Journal of Applied Physics |volume=89 |issue=11 |pages=6453–6458 |doi=10.1063/1.1361244 |issn=0021-8979}}</ref>. In the past these models were used extensively, but the complexity of modern devices makes them inadequate for quantitative design. Nonetheless, they find a place in hand analysis (that is, at the conceptual stage of circuit design), for example, for simplified estimates of signal-swing limitations.
====Empirical models====
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