Power Processing Element: Difference between revisions

Revision as of 22:44, 27 February 2023

Revision as of 22:51, 27 February 2023

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* 32 KB [[CPU cache|L1 data cache]]

* 512 KB unified L2 cache, [[Set-associative#Associativity|8-way set associative]] in the PPE variant.

* Compatible with 64-bit PowerPC ISA v.2.02 ([[POWER4]] and [[PowerPC 970]])<ref name="the-ppe">{{cite book |last1url=Koranne |first1=Sandeephttps://link.springer.com/chapter/10.1007/978-1-4419-0308-2_2 |title=Practical ProgrammingComputing on the Cell Broadband Engine |datefirst=2009Sandeep |publisherlast=SpringerKoranne Science|chapter-url=https://link.springer.com/chapter/10.1007/978-1-4419-0308-2_2 &|chapter=Chapter Business2 Media- The Power Processing Element (PPE) |isbn=9781441903082978-1-4419-0307-5 |pagepublisher=17[[Springer Science+Business Media]] |date=July 15, 2009}}</ref>{{rp|page=17}}

* [[AltiVec]] [[SIMD]] functionality

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== Multithreading ==

{{main | Simultaneous multithreading}}

The PPU runs two [[Thread_(computing)|hardware threads]] simultaneously. The [[Processor register|main registers]] for code execution are duplicated, as are the exception and interrupt-handling registers, and several essential arrays and queues. They can generate exceptions simultaneously, and perform branch prediction on their individual branch histories. The execution engine and caches are not duplicated though - so it is still just a single-core design.<ref>{{cite book |urlname= https://link.springer.com/chapter/10.1007/978-1-4419-0308-2_2 |title=Practical Computing on "the Cell Broadband Engine |first=Sandeep |last=Koranne |chapter-url=https://link.springer.com/chapter/10.1007/978-1-4419-0308-2_2 |chapter=Chapter 2 - The Power Processing Element (PPE) |isbn=978-1-4419-0307-5 |publisher=[[Springer Science+Business Media]] |date=July 15, 2009}}</refppe">

== Floating point capacity ==