Power Processing Element: Difference between revisions

Revision as of 22:51, 27 February 2023

Revision as of 23:06, 27 February 2023

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The PPU is an in-order processor, but it has some unique traits which allow it to achieve some benefits of out-of-order execution without expensive re-ordering hardware. Upon reaching an L1 cache miss - it can execute past the cache miss, stopping only when an instruction is actually dependent on a load. It can send up to 8 load instructions to the L2 cache out-of-order. It has an instruction delay pipe - a side path that allows it to execute instructions that would normally cause [[Bubble (computing)|pipeline stalls]] without holding up the rest of the [[Instruction pipeline|pipeline]]. The instruction delay pipeline is used for the Out-Of-Order Load/Stores: cache misses are put there while it moves on.

== The PPE's Pipelinepipeline ==

The PPE has a 23 stage general pipeline with an additional 11 stages possible for Microcodemicrocode and an additional 4 stages possible for Branchbranch Predictionprediction. <ref>[https://web.archive.org/web/20151208051244/http://www.ibm.com/developerworks/library/pa-cellperf/ Cell Broadband Engine Architecture and its first implementation]</ref>

== Multithreading ==