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[[File:X87 FPUs.jpg|Collection of the x87 family of math coprocessors by Intel|thumb|180px]]
A '''floating-point unit''' ('''FPU''', colloquially a '''math coprocessor''') is a part of a [[computer]] system specially designed to carry out operations on [[Floating-point arithmetic|floating-point]] numbers.<ref>{{Cite journal |author-last1=Anderson |author-first1=Stanley F. |author-last2=Earle |author-first2=John G. |author-last3=Goldschmidt |author-first3=Robert Elliott |author-last4=Powers |author-first4=Don M. |date=January 1967 |title=The IBM System/360 Model 91: Floating-Point Execution Unit |journal=[[IBM Journal of Research and Development]] |volume=11 |issue=1 |pages=34–53 |doi=10.1147/rd.111.0034 |issn=0018-8646}}</ref> Typical operations are [[addition]], [[subtraction]], [[multiplication]], [[division (mathematics)|division]], and [[square root]]. Some FPUs can also perform various [[transcendental function]]s such as [[Exponential function|exponential]] or [[trigonometric]] calculations, but the accuracy can be very low,<ref>{{cite web |url=https://randomascii.wordpress.com/2014/10/09/intel-underestimates-error-bounds-by-1-3-quintillion/ |title=Intel Underestimates Error Bounds by 1.3 quintillion |author=Bruce Dawson |website=randomascii.wordpress.com | date=2014-10-09|access-date=2020-01-16}}</ref><ref>{{cite web |url=https://software.intel.com/en-us/blogs/2014/10/09/fsin-documentation-improvements-in-the-intel-64-and-ia-32-architectures-software |title=FSIN Documentation Improvements in the "Intel® 64 and IA-32 Architectures Software Developer's Manual" |website=intel.com | date=2014-10-09|access-date=2020-01-16}}{{404}}</ref> so that some systems prefer to compute these functions in software.
In general-purpose [[computer architecture]]s, one or more FPUs may be integrated as [[execution unit]]s within the [[central processing unit]]; however, many [[embedded processor]]s do not have hardware support for floating-point operations (while they increasingly have them as standard, at least 32-bit ones).
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