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Line 17: == SSI design == The interface has a straightforward design ~~as illustrated in the above figure~~. It consists of 2 pairs of wires, one for transmitting the clock signals from the master and the other for transmitting the data from the slave. The clock sequences are triggered by the master when the need arises. Different clock frequencies can be used, ranging from 100 kHz to 2 MHz and the number of clock pulses depends on the number of data bits to be transmitted. The most straightforward SSI slave interface uses a re-triggerable monostable [[multivibrator]] (monoflop) to freeze the current value of the sensor. The current frozen values of the slave are stored in Shift registers. These values are clocked out sequentially when initiated by the controller. The design is being revolutionized by integrating microcontrollers, FPGAs and ASICs into the interface.

Synchronous Serial Interface: Difference between revisions