Display Data Channel: Difference between revisions

Revision as of 04:35, 26 April 2023

Revision as of 20:34, 4 May 2023

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More elaborate schemes also existed that used all of the 4 ID pins while manipulating the HSync and VSync signals in order to extract 16 bits (4 ID pin values for each of the 4 combinations of HSync and VSync states) of monitor identification.<ref>{{Cite web|url=http://archive.org/details/bitsavers_ibmpccardseferenceManualMay92_1756350|title=ibm :: pc :: cards :: IBM VGA XGA Technical Reference Manual May92|date=May 25, 1992|via=Internet Archive}}</ref>

DDC changed the purpose of the ID pins to incorporate a [[Serial communication|serial link interface]]. However, during the transition, the change was not backwards-compatible and video cards using the old scheme could have problems if a DDC-capable monitor was connected.<ref>[ftp://ftp.cis.nctu.edu.tw/pub/csie/Software/X11/private/VeSaSpEcS/VESA_Document_Center_Monitor_Interface/EDDCv1r1.pdf Enhanced Display Data Channel Standard, Version 1.1]{{dead link|date=September 2017 |bot=InternetArchiveBot |fix-attempted=yes }}</ref><ref>{{Cite web|url=https://www.eevblog.com/forum/projects/i2c-over-cat5e-problem/?action=dlattach;attach=185318|format=PDF|title=Enhanced Display Data Channel Standard, Version 1.1|date=March 24, 2004|access-date=2023-05-04|archive-url=http://web.archive.org/web/20230504201124/https://www.eevblog.com/forum/projects/i2c-over-cat5e-problem/?action=dlattach;attach=185318|archive-date=2023-05-04|url-status=live}}</ref> The DDC signal can be sent to or from a video graphics array (VGA) monitor with the I²C protocol using the master's serial clock and serial data pins.

===DDC1===