Advanced Programmable Interrupt Controller: Difference between revisions

Revision as of 13:01, 25 December 2022

Revision as of 04:53, 14 May 2023

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==Discrete APIC==

The first-generation Intel APIC chip, the 82489DX, which was meant to be used with [[Intel 80486]] and early Pentium processors, is actually an external local and I/O APIC in one circuit. The Intel MP 1.4 specification refers to it as "discrete APIC" in contrast with the "integrated APIC" found in most of the Pentium processors.<ref>[http://www.intel.com/design/archives/processors/pro/docs/242016.htm Intel MultiProcessor Specification], version 1.4, page 1-4, May 1997</ref> The 82489DX had 16 interrupt lines;<ref name="Ram2001">{{cite book|author=Badri Ram|title=Adv Microprocessors Interfacing|url=https://books.google.com/books?id=eVcEWDIeTYcC&pg=PT314|year=2001|publisher=Tata McGraw-Hill Education|isbn=978-0-07-043448-6|page=314}}</ref> it also had a quirk that it could lose some ISA interrupts.<ref >{{cite web | website=freebsd.org|title=A Description of the APIC I/O Subsystem | url=http://people.freebsd.org/~fsmp/SMP/papers/apicsubsystem.txt {{Bare URL plain text| access-date=March14 May 20222023}}</ref>

In a multiprocessor 486 system, each CPU had to be paired with its own 82489DX; additionally a supplementary 82489DX had to be used as I/O APIC. The 82489DX could not emulate the 8259A (XT-PIC) so these also had to be included as physical chips for backwards compatibility.<ref>Intel MultiProcessor Specification, version 1.4, page 5-3, May 1997</ref> The 82489DX was a packaged as a 132-pin [[PQFP]].<ref name="Ram2001"/>

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Another advantage of the local APIC is that it also provides a high-resolution (on the order of one [[microsecond]] or better) timer that can be used in both interval and one-off mode.<ref name="timer">Uwe Walter, Vincent Oberle [http://telematics.tm.kit.edu/publications/Files/61/walter_ibm_linux_challenge.pdf μ-second precision timer support for the Linux kernel]</ref>

The APIC timer had its initial acceptance woes. A Microsoft document from 2002 (which advocated for the adoption of [[High Precision Event Timer]] instead) criticized the LAPIC timer for having "poor resolution" and stating that "the clocks silicon is sometimes very buggy".<ref>[http://msdn.microsoft.com/en-us/library/windows/hardware/gg463347.aspx Guidelines For Providing Multimedia Timer Support], September 20, 2002</ref> Nevertheless, the APIC timer is used for example by [[Windows 7]] when [[Profiling (computer programming)|profiling]] is enabled, and by [[Windows 8]] in all circumstances. (Before Windows 8 claimed exclusive rights to this timer, it was also used by some programs like [[CPU-Z]].) Under Microsoft Windows the APIC timer is not a shareable resource.<ref>[http{{Cite web|url=https://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk Windows 8 and APIC timer] {{webarchive |archive-url=https://web.archive.org/web/20140222070735/http://social.msdn.microsoft.com/Forums/windowsdesktop/en-US/5d075378-a45f-433b-a3f7-73f974ec962f/windows-8-and-apic-timer?forum=wdk|url-status=dead|title=Windows 8 and APIC timer|archive-date=February 22, February 2014|website=social.msdn.microsoft.com|access-date=14 May 2023}}</ref>

The aperiodic interrupts offered by the APIC timer are used by the [[Linux kernel]] [[tickless kernel]]

feature. This optional but default feature is new with 2.6.18. When enabled on a computer with an APIC timer, the kernel does not use the [[8253]] [[programmable interval timer]] for timekeeping.<ref>{{cite web|url=http://kb.vmware.com/selfservice/microsites/search.do?language=en_US&cmd=displayKC&externalId=1005802|title=VMware Knowledge Base|website=kb.vmware.com}}</ref> A [[VMware]] document notes that "software does not have a reliable way to determine its frequency. Generally, the only way to determine the local APIC timer’s frequency is to measure it using the PIT or CMOS timer, which yields only an approximate result."<ref name="vmware">[http://www.vmware.com/files/pdf/Timekeeping-In-VirtualMachines.pdf Timekeeping in VMware Virtual Machines (for VMware vSphere 5.0, Workstation 8.0, Fusion 4.0)], page 8</ref>

==I/O APICs==

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The improved interface reduces the number of needed APIC register accesses for sending [[inter-processor interrupt]]s (IPIs). Because of this advantage, [[Kernel-based Virtual Machine|KVM]] can and does emulate the x2APIC for older processors that do not physically support it, and this support is exposed from [[QEMU]] going back to [[Conroe (microprocessor)|Conroe]] and even for AMD [[Opteron]] G-series processors (neither of which natively support x2APIC).<ref>{{cite web|url=https://lists.gnu.org/archive/html/qemu-devel/2013-07/msg03756.html|title=Re: [Qemu-devel] [Question] why x2apic's set by default without host sup|website=lists.gnu.org}}</ref><ref>{{cite web|url=http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg02441.html|title=[Qemu-devel] [PATCH] target-i386: enable x2apic by default on more recen|website=lists.nongnu.org}}</ref>

[[APICv]] is the Intel's brand name for [[hardware virtualization]] support aimed at reducing interrupt overhead in guests. APICv was introduced in the [[Ivy Bridge-EP]] processor series, which is sold as Xeon E5-26xx v2 (launched in late 2013) and as Xeon E5-46xx v2 (launched in early 2014).<ref>{{cite web |author=Jun Nakajima |title=Reviewing Unused and New Features for Interrupt/APIC Virtualization |url=http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-intel-vt-feat-nakajima.pdf {{Bare|website=Linux URL PDF|access-date=January14 2022May 2023 |year=2012}}</ref><ref>{{cite web|url=https://software.intel.com/en-us/blogs/2013/12/17/apic-virtualization-performance-testing-and-iozone|title=APIC Virtualization Performance Testing and Iozone* - Intel® Software|website=software.intel.com}}</ref><ref>http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/xeon-e5-4600-v2-brief.pdf {{Bare URL PDF|date=January 2022}}</ref> AMD announced a similar technology called [[Advanced Virtual Interrupt Controller|AVIC]],<ref>Wei Huang, [http://www.slideshare.net/xen_com_mgr/introduction-of-amd-virtual-interrupt-controller Introduction of AMD Advanced Virtual Interrupt Controller], XenSummit 2012</ref><ref>{{cite web |author=Jörg Rödel |title=Next-generation Interrupt Virtualization for KVM |url=http://www.linuxplumbersconf.org/2012/wp-content/uploads/2012/09/2012-lpc-virt-interrupt-virt-kvm-roedel.pdf {{Bare|website=Linux URL|access-date=14 May 2023 PDF|date=JanuaryAugust 20222012}}</ref> it is available family [[Excavator (microarchitecture)|15h models 6Xh (Carrizo) processors]] and newer.<ref>{{cite web|url=https://www.mail-archive.com/[e-mail]/msg81719.html|title=[Xen-devel] [RFC PATCH 0/9] Introduce AMD SVM AVIC|website=www.mail-archive.com}}</ref>

== Issues ==