Pass transistor logic: Difference between revisions

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In [[electronics]], '''pass transistor logic''' (PTL) describes several [[logic family|logic families]] used in the design of [[integrated circuit]]s. It reduces the count of transistors used to make different [[logic gate]]s, by eliminating redundant transistors. Transistors are used as switches to pass [[logic level]]s between nodes of a circuit, instead of as switches connected directly to supply voltages.<ref>{{cite book |first1=Jaume |last1=Segura |first2=Charles F. |last2=Hawkins |title=CMOS electronics: how it works, how it fails |publisher=Wiley-IEEE |date=2004 |isbn=0-471-47669-2 |pages=132 |url=}}</ref> This reduces the number of active devices, but has the disadvantage that the difference of the voltage between high and low logic levels decreases at each stage (since pass transistors have some resistance and do not provide level restoration). Each transistor in series is less saturated at its output than at its input.<ref>{{cite book |first=Clive |last=Maxfield |title=Bebop to the boolean boogie: an unconventional guide to electronics |publisher=Newnes |date=2008 |isbn=978-1-85617-507-4 |pages=423–6 |url=}}</ref> If several devices are chained in series in a logic path, a conventionally constructed gate may be required to restore the signal voltage to the full value. By contrast, conventional [[CMOS logic]] switches transistors so the output connects to one of the power supply rails (resembling an [[open collector]] scheme), so logic voltage levels in a sequential chain do not decrease.

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Simulation of circuits may be required to ensure adequate performance.

== Applications ==

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==Basic principles of pass transistor circuits==

MOSFET pass transistors are [[Electronic switch|electronic switches]] that turn on or off the path between their drain and source depending on their gate's voltage signal (for instance the clock signal in the [[Static random-access memory|SRAM]] cell or [[gated D latch]]).

The pass transistor is driven by a periodic clock signal and acts as an access switch to either charge up or charge down the parasitic capacitance C_''x'', depending on the input signal V_''in''. Thus there are two possible operations , when the clock signal is active (CK = 1) are the logic "1" transfer (charging up the capacitance C_''x'' to a logic-high level) and the logic "0" transfer (charging down the capacitance C_''x'' to a logic-low level). In either case, the output of the depletion load nMOS inverter obviously assumes a logic-low or a logic-high level, depending upon the voltage V_''x''.

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Because pass transistors do not provide level restoration and because their conducting path has a small non-zero resistance, there is increased [[RC delay]] for charging the next logic stage's input capacitance (which includes parasitic capacitance in addition to the next stage's gate capacitance) towards valid logic-high or logic-low voltage levels.

Simulation of circuits may be required to ensure adequate performance.

=={{anchor|CPL}}Complementary pass transistor logic==