Parallel SCSI: Difference between revisions

Revision as of 19:48, 6 June 2023

Revision as of 19:52, 6 June 2023

Line 35:

! rowspan=3 | Connector

! rowspan=3 | Width (bits)

! rowspan=3 | Clock{{efn-ua|group=Comparison|Clock rate in ([[hertz|MHz]] for SPI, or [[bitrate]] (per second) for serial interfaces.}}

! colspan=6 | Maximum

! colspan=2 | Electrical

Line 45:

! rowspan=2 | Voltage ([[Volt|V]])

|-

! ([[MB/s]])

! ([[Mbit/s]])

! Single ended{{efn-ua|group=Comparison|For daisy-chain designs, length of bus, from end to end; for point-to-point, length of a single link.}}

! [[Low-voltage differential signaling|LVD]]{{efn-ua|LVD cabling may be up to 25 m when only a single device is attached to the host adapter, 20 m for Ultra-640.}}

Line 60:

| 40

| 6

| {{N/A|N/A}}

| NA

| 25

| 8

Line 75:

| 80

| 3

| {{N/A|N/A}}

| NA

| 25

| 8

Line 90:

| 160

| 3

| {{N/A|N/A}}

| NA

| 25

| 16

Line 105:

| rowspan=2 | 160

| 1.5

| {{N/A|N/A}}

| NA

| 25

| 8

Line 112:

|-

| 3

| {{N/A|N/A}}

| NA

| {{N/A|N/A}}

| NA

| 4

|-

Line 124:

| rowspan=3 | 40 MB/s

| rowspan=3 | 320 Mbit/s

| {{N/A|N/A}}

| NA

| {{N/A|N/A}}

| NA

| 25

| 16

Line 132:

|-

| 1.5

| {{N/A|N/A}}

| NA

| {{N/A|N/A}}

| NA

| 8

|-

| 3

| {{N/A|N/A}}

| NA

| {{N/A|N/A}}

| NA

| 4

|-

Line 149:

| 40

| 320

| {{N/A|N/A}}

| NA

| 12

| 25

Line 164:

| 80

| 640

| {{N/A|N/A}}

| NA

| 12

| 25

Line 179:

| 160

| 1280

| {{N/A|N/A}}

| NA

| 12

| {{N/A|N/A}}

| NA

| 16

| {{nowrap| [[Low-voltage differential signaling|LVD]] 125 ± 10<ref name="random"/> }}

Line 194:

| 320

| 2560

| {{N/A|N/A}}

| NA

| 12

| {{N/A|N/A}}

| NA

| 16

| {{nowrap| [[Low-voltage differential signaling|LVD]] 125 ± 10<ref name="random"/> }}

Line 209:

| 640

| 5120

| {{N/A|N/A}}

| NA

| 10

| {{N/A|N/A}}

| NA

| 16

| {{nowrap| LVD 125 ± 10}}