Manycore processing unit: Difference between revisions

Revision as of 06:03, 1 March 2007

Revision as of 13:10, 18 March 2007

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=== Integrated streaming packet IO hardware ===

[[Embedded systems|Embedded]] packet processing and network control applications have heavy packet [[Input/output|IO]] loads so many MPUs add streaming packet interface functions in on-chip [[Computer hardware|hardware]] to offload these tasks from [[software]] on the processor cores. [[Data link layer|Layer-two]] [[Communications protocol|protocol]] termination (e.g. [[Ethernet]] [[Media Access Control|MAC]] layer) in hardware combined with packet [[Input/output|input and output]] packet [[Queue (data structure)|queues]] are typical. This is compared with general purpose processors that normally use memory address-space oriented [[Interface (computer science)|interfaces]] such as [[PCI]], [[PCI-Express]] or [[Hypertransport]].

=== Packet processing acceleration hardware ===