Revision as of 03:10, 19 June 2023 edit Sbmeirow (talk \| contribs) Extended confirmed users, Rollbackers 122,815 edits →Debug and trace probes: case ← Previous edit		Revision as of 03:26, 19 June 2023 edit undo Sbmeirow (talk \| contribs) Extended confirmed users, Rollbackers 122,815 edits →Debug and trace probes: clarify Next edit →
Line 27: \|+ <big>J-Trace & J-Link Models</big><ref>[http://www.segger.com/jlink-model-overview.html J-Link Model Overview; segger.com]</ref> \|- ! Model !! Host<br/>[[USB#Version history\|USB]] !! Host<br/>[[Ethernet physical layer\|Ethernet]] !! Host<br/>[[Wi-Fi]] !! ~~Target~~Debug<br/>[[Pin header\|connector]] !! Trace<br/>[[Pin header\|connector]] !! Target<br/>[[volt]]age !! Target max<br/>interface<br/>speed !! Target max<br/>download<br/>speed !! Target<br/>[[Virtual COM port\|VCOM]]<br/>[[Universal asynchronous receiver-transmitter\|UART]] !! Software<br/>features \|- \| '''J-Trace''' PRO Cortex-A/R/M \|\| 3.0 SS \|\| {{yes\|1 Gbit/s}} \|\| None \|\| 20-pin 0.1" \|\| {{yes\|19-pin 0.05"}} \|\| 1.2V to 5V \|\| 50 [[MHz]] \|\| 3 MByte/s \|\| 2 pins \|\| All

Segger Microcontroller Systems: Difference between revisions