Talk:Complex instruction set computer: Difference between revisions

Revision as of 02:39, 24 June 2023

Revision as of 05:27, 24 June 2023

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This article is mostly personal opinion and original research, rather than information from reliable sources. For example, the article equates RISC with load-store architecture, which doesn't match published RISC definitions. This ahistorical definition then leads to strange conclusions such as the Intel 4004 is a CISC. While it would be nice to have an easy definition where combining arithmetic and memory access = CISC, that's not the case. I could be [[WP:BOLD]] and delete all the uncited statements, but there wouldn't be much left, so I'm encouraging people to cite reliable sources. [[User:KenShirriff|KenShirriff]] ([[User talk:KenShirriff|talk]]) 02:39, 24 June 2023 (UTC)

:Is RISC ''currently'' being used in any technical sense other than "load/store architecture"? (It is often used as a ''marketing'' term, as in "CISC: tired; RISC: wired", but that's another matter.)

:"Doesn't use microcode" isn't that meaningful a definition of "RISC" any more. The [[Honeywell 6000]] series was hardwired but had some Pretty Complex Instructions, especially in machines with the EIS box, and the [[IBM System/360 Model 75]] was hardwired and implemented the full S/360 instruction set, complete with decimal arithmetic, ED/EDMK, TRT, etc. Furthermore, I'm not sure any current [[z/Architecture]] processors have anything that would be considered "microcode" - they have [[millicode]], but that is, as I understand it, closer to [[PALcode]], and apparently also have "i370"/"i390" code, which is somewhere above millicode but still used to implement some architectural features; both of them are subsets of z/Architecture machine code, with millicode being able to execute special chip-dependent instructions to peform certain functions. The [[Intel 80486]] executed some instructions directly in hardware; in the Pentium Pro and later, I have the impression that the microcode engine generates [[micro-operations]] that go into the same scheduler as the micro-operations generated by the instruction decoder.

:"All instructions take one clock tick" doesn't work any more unless you have not only a one-cycle combinatorial multiplier but a one-cycle combinatorial divider, given that many "RISC" instruction sets have integer multiply and divide and floating-point multiply and divide instructions.

:"Fixed-length instructions" may work better, but at least some architectures that are called "RISC" have compressed instructions (Thumb/Thumb-2/T2, whatever they're called in Power ISA, whatever RISC-V calls it).

:"No complex instructions" might work, but requires a definition of "complicated", and S/360, for example, may have had ED/EDMK (probably the most complicated instruction, both from the description and from the "is this just an attempt to turn some programming language construct into a single instruction?" notion), but its procedure call instructions BAL/BALR are rather close to the ones most RISC processors have (stuff next instruction PC into a register and jump; leave it up to whoever or whatever generates the code for the called instruction to decide what else to do). "No complex addressing modes" is similar, unless you consider double-indexing, present in both x86 and S/3x0, "too complex for RISC".

:And as for "CISC", as the article notes, it was coined retroactively, pretty much meaning "not RISC"; if "RISC" is interpreted sufficiently narrowly, "CISC" would then cover a rather wide range.

:So, yes, if there are widely-accepted (with sources to demonstrate the wide acceptance) definitions of RISC and CISC, that'd work, but, absent that, I'm not sure what could be done here. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 05:27, 24 June 2023 (UTC)