Content deleted Content added
adding Stanford Hydra (a highly notable academic CMP); removing wikilink to unrelated article on a different Kilocore CPU |
RP2040 |
||
Line 1:
{{Short description|Microprocessor with more than one processing unit}}
{{Redirect|Dual Core|the nerdcore duo|Dual Core (hip hop duo)}}
[[File:Dual Core Generic.svg|thumb
[[File:E6750bs8.jpg|thumb
[[File:Athlon64x2-6400plus.jpg|thumb
A '''multi-core processor''' is a [[microprocessor]] on a single [[integrated circuit]] with two or more separate [[Central processing unit|processing units]], called cores, each of which reads and executes [[Instruction set|program instructions]].<ref>{{cite web|url= http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html|publisher= TechTarget|title= Definition: multi-core processor|last= Rouse|first= Margaret|date= March 27, 2007|access-date= March 6, 2013|url-status= dead|archive-url= https://web.archive.org/web/20100805052158/http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html|archive-date= August 5, 2010}}</ref> The instructions are ordinary [[Instruction set|CPU instructions]] (such as add, move data, and branch) but the single processor can run instructions on separate cores at the same time, increasing overall speed for programs that support [[Multithreading (computer architecture)|multithreading]] or other [[parallel computing]] techniques.<ref>{{cite web|url=http://www.csa.com/discoveryguides/multicore/review.pdf|title=Multicore Processors – A Necessity|last=Schauer|first=Bryan|archive-url=https://web.archive.org/web/20111125035151/http://www.csa.com/discoveryguides/multicore/review.pdf|archive-date=2011-11-25}}</ref> Manufacturers typically integrate the cores onto a single integrated circuit [[Die (integrated circuit)|die]] (known as a chip multiprocessor or CMP) or onto multiple dies in a single [[Chip carrier|chip package]]. The microprocessors currently used in almost all personal computers are multi-core.
Line 60:
The proximity of multiple CPU cores on the same die allows the [[cache coherency]] circuitry to operate at a much higher clock rate than what is possible if the signals have to travel off-chip. Combining equivalent CPUs on a single die significantly improves the performance of [[cache snooping|cache snoop]] (alternative: [[Bus snooping]]) operations. Put simply, this means that [[Discrete signal|signals]] between different CPUs travel shorter distances, and therefore those signals [[Degradation (telecommunications)|degrade]] less. These higher-quality signals allow more data to be sent in a given time period, since individual signals can be shorter and do not need to be repeated as often.
Assuming that the die can physically fit into the package, multi-core CPU designs require much less [[printed circuit board]] (PCB) space than do multi-chip [[symmetric multiprocessing|SMP]] designs. Also, a dual-core processor uses slightly less power than two coupled single-core processors, principally because of the decreased power required to drive signals external to the chip. Furthermore, the cores share some circuitry, like the L2 cache and the interface to the [[front-side bus]] (FSB). In terms of competing technologies for the available silicon die area, multi-core design can make use of proven CPU core library designs and produce a product with lower risk of design error than devising a new wider-core design. Also, adding more cache suffers from diminishing returns.
Multi-core chips also allow higher performance at lower energy. This can be a big factor in mobile devices that operate on batteries. Since each core in a multi-core CPU is generally more energy-efficient, the chip becomes more efficient than having a single large monolithic core. This allows higher performance with less energy. A challenge in this, however, is the additional overhead of writing parallel code.<ref>{{cite web|title=Q & A: Do multicores save energy? Not really.|url=http://www.futurechips.org/chip-design-for-all/a-multicore-save-energy.html|last=Suleman|first=Aater|date=May 19, 2011|access-date=March 6, 2013|url-status=dead|archive-url=https://web.archive.org/web/20121216051010/http://www.futurechips.org/chip-design-for-all/a-multicore-save-energy.html|archive-date=December 16, 2012}}</ref>
Line 186:
** Vega 2, a 48-core processor, released in 2006.
** Vega 3, a 54-core processor, released in 2008.
* Broadcom
* Broadcom SiByte SB1250, SB1255, SB1455; BCM 2836 quad-core ARM SoC (designed for the [[Raspberry Pi]] 2)▼
** SiByte SB1250, SB1255, SB1455
▲**
* [[Cadence Design Systems]] [[Tensilica]] Xtensa LX6, available in a dual-core configuration in [[Espressif Systems]]'s [[ESP32]]
* [[ClearSpeed]]
Line 199 ⟶ 201:
** [[POWER5]], a dual-core PowerPC processor, released in 2004.
** [[POWER6]], a dual-core PowerPC processor, released in 2007.
** [[POWER7]], a 4, 6
** [[POWER8]], a 12-core PowerPC processor, released in 2013.
** [[POWER9]], a 12 or 24-core PowerPC processor, released in 2017.
Line 212 ⟶ 214:
** [[IBM z15 (microprocessor)|z15]], a twelve-core z/Architecture processor, released in 2019.
** [[IBM Telum (microprocessor)|Telum]], an eight-core z/Architecture processor, released in 2021.
* [[Infineon]]
** [[Infineon AURIX|AURIX]]
Line 244 ⟶ 245:
* [[Plurality (company)|Plurality]] HAL series tightly coupled 16-256 cores, L1 shared memory, hardware synchronized processor.
* Rapport [[Kilocore]] KC256, a 257-core microcontroller with a PowerPC core and 256 8-bit "processing elements".
* Raspberry Pi Ltd. [[RP2040]], a dual [[ARM Cortex-M0+]] [[microcontroller]]
* [[SiCortex]] "SiCortex node" has six MIPS64 cores on a single chip.
* [[SiFive]]
Line 260 ⟶ 262:
* [[Texas Instruments]]
** [[Texas Instruments TMS320|TMS320C80 MVP]], a five-core multimedia video processor.
** TMS320TMS320C66, 2-, 4-,
* [[Tilera]]
** [[TILE64]], a 64-core 32-bit processor.
| |||