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KenShirriff (talk | contribs) |
Guy Harris (talk | contribs) →Many dubious and unsourced claims: Point to a sequence of John Mashey comp.arch posts on the topic. |
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:::Thus, one has to accept that RISC and CISC never had nice, clean definitions and describe that with a [[WP:NPOV]] rather than trying to invent the One True Definition.
:::[[User:KenShirriff|KenShirriff]] ([[User talk:KenShirriff|talk]]) 18:03, 24 June 2023 (UTC)
::::BTW, [http://www.righto.com/2023/07/the-complex-history-of-intel-i960-risc.html your post on the 960] pointed to [https://yarchive.net/comp/risc_definition.html this sequence of John Mashey comp.arch posts], which is somewhat relevant here. Mashey seems to lean towards "CISC means 'not RISC'", and thinks talking about many older CPUs as "CISC" or "RISC" isn't a useful execise.
::::That's a sequence from 1992, from an era before the "throw a bunch of simple operations into a bucket and run them superscalar and out-of-order - which may involve chopping complex instructions into muliple simple operations" stuff, so it'd be interesting to see what he'd say now.
::::And the two CISC ISAs he seemed to put in the "relatively simple, as CISCs go" bucket 1) are the two remaining CISCs from that paper, 2) have a ton of money behind them (PC x86 processors and IBM mainframes), and 3) appear now to have implementations in the "throw a bunch of simple operations into a bucket and..." camp. [[User:Guy Harris|Guy Harris]] ([[User talk:Guy Harris|talk]]) 22:53, 2 July 2023 (UTC)
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