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<ref></ref>{{User sandbox}}
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In conjunction with the [[Semiconductor device|semiconductor]] boom started in the 1960s, computer architects were tasked with finding new ways to exploit the increasingly large number of transistors available. [[Moore's law|Moore's Law]] and [[Dennard scaling|Dennard Scaling]] enabled architects to focus on improving the performance of general-purpose microprocessors on general-purpose programs <ref>{{Cite journal |last=Moore |first=G.E. |date=1998-01 |title=Cramming More Components Onto Integrated Circuits |url=http://dx.doi.org/10.1109/jproc.1998.658762 |journal=Proceedings of the IEEE |volume=86 |issue=1 |pages=82–85 |doi=10.1109/jproc.1998.658762 |issn=0018-9219}}</ref><ref>{{Cite journal |last=Dennard |first=R.H. |last2=Gaensslen |first2=F.H. |last3=Yu |first3=Hwa-Nien |last4=Rideout |first4=V.L. |last5=Bassous |first5=E. |last6=LeBlanc |first6=A.R. |date=1974-10 |title=Design of ion-implanted MOSFET's with very small physical dimensions |url=http://dx.doi.org/10.1109/jssc.1974.1050511 |journal=IEEE Journal of Solid-State Circuits |volume=9 |issue=5 |pages=256–268 |doi=10.1109/jssc.1974.1050511 |issn=0018-9200}}</ref>.
These efforts yielded several technological innovations such as [[Multi-level cache|multi-level caches]], [[out-of-order execution]], deep instruction [[Instruction pipelining|pipelines]], [[Multithreading (computer architecture)|multithreading]] and [[multiprocessing]]. The impact of these innovations was measured on generalist benchmarks such as [[SPEC]], and architects were not concerned with the internal structure or specific characteristics of these programs<ref name=":0">{{Cite book |last=Hennessy |first=John L. |title=Computer architecture: a quantitative approach |last2=Patterson |first2=David A. |date=2019 |publisher=Morgan Kaufmann Publishers, an imprint of Elsevier |others=Krste Asanović |page=540 |isbn=978-0-12-811905-1 |edition=Sixth edition |___location=Cambridge, Mass}}</ref>.
The end of Dennard scaling pushed computer architects to switch from a single, very fast processor to several [[Multi-core processor|processor cores]]. Performance improvement could no longer be achieved by simply increasing the operating frequency of a single core.<ref>{{Cite web |last=Schauer |first=Bryan |title=Multicore Processors – A Necessity |url=http://www.csa.com/discoveryguides/multicore/review.pdf |archive-url=https://web.archive.org/web/20111125035151/http://www.csa.com/discoveryguides/multicore/review.pdf |archive-date=2011-11-25 |access-date=2023-07-06 |website=}}</ref>
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While [[Hardware acceleration|hardware accelerators]] and [[Application-specific integrated circuit|ASIC]] have been used in very specialized application domains since the inception of the semiconductor industry, they generally implement a specific function with very limited flexibility. In contrast, the shift towards ___domain-specific architectures wants to achieve a better balance of flexibility and specialization.
A notable early example of a ___domain-specific programmable architecture are [[Graphics processing unit|GPU.]] These specialized hardware were developed specifically to operate within the ___domain of [[Digital image processing|image processing]] and [[computer graphics]]. These programmable processing units found widespread adoption both in [[Video game console|gaming consoles]] and personal computers. With the improvement of the hardware/software stack for both [[Nvidia|NVIDIA]] and [[AMD]] GPUs, these architectures are being used more and more for the acceleration of [[Embarrassingly parallel|embarassingly parallel]] tasks, even outside of the ___domain of image processing<ref>{{Cite web |title=NVIDIA Accelerated Applications |url=https://www.nvidia.com/en-us/gpu-accelerated-applications/ |access-date=2023-07-06 |website=NVIDIA |language=en-us}}</ref>.
== Guidelines for DSA Design ==
[[John L. Hennessy|John Hennessy]] and [[David Patterson (computer scientist)|David Patterson]] outlined five principles for DSA design that lead to a better area efficiency and energy savings. The objective in these types of architecture is often also to reduce the Non-Recurring Engineering (NRE) costs, so that the investment in a specialized solution can be more easily amortized<ref name=":0" />.
=== Minimize Distance over which Data is Moved ===
A remarkable amount of energy is used in general-purpose [[Memory hierarchy|memory hierarchies]] moving data attempting to minimize the latency required to access data. In the case of Domain-Specific Architectures, it is expected that understanding of the application domains by hardware and compiler designers allows for simpler and specializied memory hierarchies, where the data movement is largely handled in software, with tailor-made memories for specific functions within the ___domain.
=== Invest Saved Resources into Arithmetic Units or Bigger Memories ===
== See also ==
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