Domain-specific architecture: Difference between revisions

Revision as of 13:55, 7 July 2023

Revision as of 13:57, 7 July 2023

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=== Minimize the distance over which data is moved ===

Moving data in general-purpose [[Memory hierarchy|memory hierarchies]] requires a remarkable amount of energy in order to attempt to minimize the latency to access data. In the case of Domain-Specific Architectures, it is expected that understanding of the application domains by hardware and [[compiler]] designers allows for simpler and specialized memory hierarchies, where the data movement is largely handled in software, with tailor-made memories for specific functions within the ___domain.<ref name=":0" />

=== Invest saved resources into arithmetic units or bigger memories ===

Since a remarkable amount of hardware resources can be saved by dropping general-purpose architectural optimizations such as out-of-order execution, [[Prefetching (computing)|prefetching]], address [[Coalescing (computer science)|coalescing]], and hardware speculation, the resources saved should be re-invested to maximally exploit the available [[Parallelism (computing)|parallelism]], for example, by adding more arithmetic units, or solve any [[memory bandwidth]] issues by adding bigger memories.<ref name=":0" />

=== Use the easiest form of parallelism that matches the ___domain ===