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{{about|the general concept|its implementation found in x86 processors|Interrupt descriptor table}}
[[File:X86 Interrupt Vector Table.svg|thumb]]
An '''interrupt vector table''' ('''IVT''') is a [[data structure]] that associates a list of [[interrupt handler]]s with a list of [[interrupt request]]s in a table of interrupt vectors. Each entry of the interrupt vector table, called an interrupt vector, is the address of an interrupt handler(also known as [[Interrupt_handler|ISR]]). While the concept is common across processor architectures, IVTs may be implemented in architecture-specific fashions. For example, a [[dispatch table]] is one method of implementing an interrupt vector table.
Interrupts are assigned a number between 0 to 255. The interrupt vectors for each interrupt number are stored in the lower 1024 bytes of main memory. For example, interrupt 0 is stored from 0000:0000 to 0000:0003, interrupt 1 from 0000:0004 to 0000:0007, and so on.
==Background==
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