Content deleted Content added
Harshdaank (talk | contribs) Added info |
|||
Line 27:
<!-- I wasn't able to square-up the image when measuring dimensions off screen, since I only had area, but not W*H so these are a little more approx. than they might have been; I had W*H for the included SPU but the top four SPU measure differently than the bottom four in the way they overdrew the boundaries, leaving me with the same problem -->
{| class="wikitable"
|+ Cell function units and footprint
! Cell function unit !! Area
|-
| XDR interface || {{0}}5.7% || Interface to Rambus system memory
|-
| memory controller || {{0}}4.4% || Manages external memory and L2 cache
|-
| 512 KiB L2 cache || 10.3% || Cache memory for the PPE
|-
| PPE core || 11.1% || PowerPC processor
|-
| test || {{0}}2.0% || Unspecified "test and decode logic"
|-
| EIB || {{0}}3.1% || Element interconnect bus linking processors
|-
| SPE (each) × 8 || {{0}}6.2% || Synergistic coprocessing element
|-
| I/O controller || {{0}}6.6% || External I/O logic
|-
| Rambus FlexIO || {{0}}5.7% || External signalling for I/O pins
|}
| |||