Segger Microcontroller Systems: Difference between revisions

Revision as of 02:52, 8 August 2023

Revision as of 05:34, 8 August 2023

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==Product categories==

===Debug and trace probes===

[[File:Segger J-Trace Cortex-M.jpg|thumb|right|J-Trace PRO Cortex-M]]

[[File:Segger J-Link PRO.jpg|thumb|right|J-Link PRO with [[USB]] and [[Ethernet]] host interfaces]]

Segger is most noted for its J-Link family, which supports [[JTAG]] (Joint Test Action Group) and SWD (Serial Wire Debug) debug probes for microcontrollers that have older ARM cores ([[ARM7]], [[ARM9]], [[ARM11]]), ARM Cortex-M cores ([[ARM Cortex-M0|M0]], [[ARM Cortex-M0+|M0+]], [[ARM Cortex-M1|M1]], [[ARM Cortex-M3|M3]], [[ARM Cortex-M4|M4]], [[ARM Cortex-M7|M7]], [[ARM Cortex-M23|M23]], [[ARM Cortex-M33|M33]], M85), ARM Cortex-R cores ([[ARM Cortex-R4|R4]], [[ARM Cortex-R5|R5]], [[ARM Cortex-R8|R8]]), ARM Cortex-A cores ([[ARM Cortex-A5|A5]], [[ARM Cortex-A7|A7]], [[ARM Cortex-A8|A8]], [[ARM Cortex-A9|A9]], [[ARM Cortex-A12|A12]], [[ARM Cortex-A15|A15]], [[ARM Cortex-A17|A17]], A53, A72), [[Renesas RX]], Microchip [[PIC32]], SiLab EFM8, [[RISC-V]].<ref>[http://www.segger.com/cms/development-tools.html Segger J-Link Product Line]</ref> It is also repackaged and sold as an OEM item<ref>[http://www.edn.com/article/CA6301710.html Advertisement<!-- Bot generated title -->]</ref> by [[Analog Devices]] as the mIDASLink, [[Atmel]] as the SAM-ICE, [[Digi International]] as the Digi JTAG Link, and [[IAR Systems]] as the J-Link and the J-Link KS. This is the only JTAG emulator that can add Segger's patented flash breakpoint software to a debugger to enable the setting of multiple breakpoints in flash while running on an ARM device which is typically hindered by the limited availability of hardware breakpoints.<ref>[http://www.circuitcellar.com/library/newproducts/180/segger.htm Circuit Cellar - Digital Library - New Product News<!-- Bot generated title -->] {{webarchive|url=https://web.archive.org/web/20070311133130/http://www.circuitcellar.com/library/newproducts/180/segger.htm |date=2007-03-11 }}</ref>

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| style="text-align:left" | J-Trace PRO RISC-V || 3.0 SS || {{yes|1 Gbit/s}} || None || 20-pin 0.1" || {{yes|19-pin 0.05"}} || 1.2V to 5V || 50&nbsp;MHz || 3 MByte/s || 2 pins || All || [[File:J-Trace RISC-V 1349x1466.png|95px]]

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| style="text-align:left" | '''J-Link''' PRO || 2.0 HS || {{yes|100 Mbit/s}} || None || 20-pin 0.1" || None || 1.2V to 5V || 50&nbsp;MHz || 3 MByte/s || 2 pins || All || [[File:J-Link PRO 1349x1466.png|95px]]

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| style="text-align:left" | J-Link BASE || 2.0 HS || None || None || 20-pin 0.1" || None || 1.2V to 5V || 15&nbsp;MHz || 1 MByte/s || 2 pins || Limited || [[File:J-Link BASE Classic 1349x1466.png|95px]]

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| style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} <!-- NOTE - grouping divider -->

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| style="text-align:left" | J-Link EDU || 2.0 HS || None || None || 20-pin 0.1" || None || 1.2V to 5V || 15&nbsp;MHz || 1 MByte/s || 2 pins || Limited || [[File:J-Link EDU 1349x1466.png|95px]]