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==Product categories==
===Debug and trace probes===
Segger is most noted for its J-Link family, which supports [[JTAG]] (Joint Test Action Group) and SWD (Serial Wire Debug) debug probes for microcontrollers that have older ARM cores ([[ARM7]], [[ARM9]], [[ARM11]]), ARM Cortex-M cores ([[ARM Cortex-M0|M0]], [[ARM Cortex-M0+|M0+]], [[ARM Cortex-M1|M1]], [[ARM Cortex-M3|M3]], [[ARM Cortex-M4|M4]], [[ARM Cortex-M7|M7]], [[ARM Cortex-M23|M23]], [[ARM Cortex-M33|M33]], M85), ARM Cortex-R cores ([[ARM Cortex-R4|R4]], [[ARM Cortex-R5|R5]], [[ARM Cortex-R8|R8]]), ARM Cortex-A cores ([[ARM Cortex-A5|A5]], [[ARM Cortex-A7|A7]], [[ARM Cortex-A8|A8]], [[ARM Cortex-A9|A9]], [[ARM Cortex-A12|A12]], [[ARM Cortex-A15|A15]], [[ARM Cortex-A17|A17]], A53, A72), [[Renesas RX]], Microchip [[PIC32]], [[Silicon Labs|SiLab]] EFM8, [[RISC-V]].<ref>[http://www.segger.com/cms/development-tools.html Segger J-Link Product Line]</ref> It is also repackaged and sold as an OEM item<ref>[http://www.edn.com/article/CA6301710.html Advertisement<!-- Bot generated title -->]</ref> by [[Analog Devices]] as the mIDASLink, [[Atmel]] as the SAM-ICE, [[Digi International]] as the Digi JTAG Link, and [[IAR Systems]] as the J-Link and the J-Link KS. This is the only JTAG emulator that can add Segger's patented flash breakpoint software to a debugger to enable the setting of multiple
{| class="wikitable nounderlines sortable" style="text-align: center;"
|+ <big>J-Trace & J-Link Models</big><ref>[http://www.segger.com/jlink-model-overview.html J-Link Model Overview; segger.com]</ref>
|-
! Model !! Host<br/>[[USB#Version history|USB]]<br /> !! Host<br/>[[Ethernet physical layer|Ethernet]]<br /> !! Host<br/>[[Wi-Fi]]<br /> !! Debug<br />[[Pin header|connector]]<br />([[Pitch (electronics)|Pitch]]) !! Trace<br/>[[Pin header|connector]]<br /> !! Target<br/>[[volt]]age<br /> !! Target max<br />interface<br />speed !! Target max<br />download<br />speed !! Target<br />[[Virtual COM port|VCOM]]<br />[[Universal asynchronous receiver-transmitter|UART]] !! Software<br />features<br /> !! Image<br /> </br >
|-
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| style="text-align:left" | J-Trace PRO Cortex-M || 3.0 SS || {{yes|1 Gbit/s}} || None || 20-pin (0.1") || {{yes|19-pin 0.05"}} || 1.2V to 5V || 50 MHz || 3 MByte/s || 2 pins || All || [[File:J-Trace Cortex-M 1349x1466.png|95px]]
|-
| style="text-align:left" | J-Trace PRO RISC-V || 3.0 SS || {{yes|1 Gbit/s}} || None || 20-pin (0.1") || {{yes|19-pin 0.05"}} || 1.2V to 5V || 50 MHz || 3 MByte/s || 2 pins || All || [[File:J-Trace RISC-V 1349x1466.png|95px]]
|-
| style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} <!-- NOTE - grouping divider -->
|-
| style="text-align:left" |
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| style="text-align:left" | J-Link ULTRA+ || 2.0 HS || None || None || 20-pin (0.1"
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| style="text-align:left" | J-Link [[WiFi]] || 2.0 HS || None || {{yes|802.11b/g/n}} || 20-pin (0.1") || None || 1.2V to 5V || 15 MHz || 1 MByte/s || 2 pins || All || [[File:J-Link Wifi 1349x1466.png|95px]]
|-
| style="text-align:left" | J-Link PLUS || 2.0 HS || None || None || 20-pin (0.1") || None || 1.2V to 5V || 15 MHz || 1 MByte/s || 2 pins || All || [[File:J-Link PLUS Classic 1349x1466.png|95px]]
|-
| style="text-align:left" | J-Link
|-
| style="text-align:left" | J-Link BASE || 2.0 HS || None || None || 20-pin (0.1") || None || 1.2V to 5V || 15 MHz || 1 MByte/s || 2 pins || Limited || [[File:J-Link BASE Classic 1349x1466.png|95px]]
|-
| style="text-align:left" | J-Link BASE Compact || 2.0 HS || None || None || 20-pin (0.1") || None || 1.2V to 5V || 15 MHz || 1 MByte/s || 2 pins || Limited || [[File:J-Link BASE-Compact 1349x1466.png|95px]]
|-
| style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} || style="background: black;" | {{sp}} <!-- NOTE - grouping divider -->
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| style="text-align:left" | J-Link EDU || 2.0 HS || None || None || 20-pin (0.1") || None || 1.2V to 5V || 15 MHz || 1 MByte/s || 2 pins || Limited || [[File:J-Link EDU 1349x1466.png|95px]]
|-
| style="text-align:left" | J-Link EDU Mini || 2.0 FS || None || None || 9-pin (0.
|-
| style="text-align:left" | J-Link OB || 2.0 FS || None || None || Integrated || None || Integrated || 4 MHz || 0.2 MByte/s || Depends || Limited ||
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* Note: The EDU & EDU Mini models cannot be used for commercial software development, also doesn't come with J-Flash, J-Flash-SPI, RDDI, RDI options.
* Note: Adapters and isolators are available to convert the 20-pin 0.1"/2.54mm [[Pin header|male shrouded (box) header]] to another target board connector.<ref>[http://www.segger.com/jlink-adapters.html J-Link adapters and isolators; segger.com]</ref>
* Note: The compact variants are functionally identical to the standard variants
==See also==
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