FPGA prototyping: Difference between revisions

Revision as of 09:57, 23 August 2022

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#Running a SoC design on FPGA prototype is a reliable way to ensure that it is functionally correct. This is compared to designers only relying on [[Electronic circuit simulation|software simulations]] to verify that their hardware design is sound. About a third of all current SoC designs are fault-free during first silicon pass, with nearly half of all re-spins caused by functional logic errors.<ref name ="soc">{{Cite web |url=http://www.soccentral.com/results.asp?CatID=596&EntryID=30794 |title=SOCcentral: Getting the Most Out of ASIC Prototyping with FPGAs (EE Times Programmable Logic Designline 30794) |access-date=October 9, 2012 |archive-url=https://archive.today/20130202104923/http://www.soccentral.com/results.asp?CatID=596&EntryID=30794 |archive-date=February 2, 2013 |url-status=dead }}</ref> A single prototyping platform can provide verification for hardware, firmware, and application software design functionality before the first silicon pass.<ref>{{Cite web|url=http://www.tayden.com/publications/Nanometer%20Prototyping.pdf|title=Nanometer prototyping|last=Rittman|first=Danny|date=2006-01-05|website=Tayden Design|access-date=2018-10-07}}</ref>

#[[Time to market|Time-to-market]] (TTM) is reduced from FPGA prototyping: In today's technological driven society, new products are introduced rapidly, and failing to have a product ready at a given [[market window]] can cost a company a considerable amount of [[revenue]].<ref name="reason">{{Cite web|url=http://www.design-reuse.com/articles/13550/fpga-prototyping-to-structured-asic-production-to-reduce-cost-risk-ttm.html|title=FPGA Prototyping to Structured ASIC Production to Reduce Cost, Risk & TTM|website=Design And Reuse|access-date=2018-10-07}}</ref> If a product is released too late of a market window, then the product could be [[Obsolescence|rendered useless]], costing the company its investment capital in the product. After the design process, FPGAs are ready for production, while [[Standard cell|standard cell ASICs]] take more than six months to reach production.<ref name = reason/>

#Development cost: Development cost of 90-nm ASIC/SoC design tape-out is around $20 million, with a mask set costing over $1 million alone.<ref name= soc/> Development costs of 45-nm designs are expected to top $40 million. With increasing cost of mask sets, and the continuous decrease of IC size, minimizing the number of re-spins is vital to the development process.